Patents by Inventor Paul K. Lai

Paul K. Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configurable transmitter device based on data rate
    Patent number: 11907004
    Abstract: A transmitter device includes a configurable timer circuit that adjusts timing of input data for serial transmission of the input data. The configurable timer circuit may be configured depending on the configured data rate of the transmitter device. In one embodiment, the configurable timer circuit includes a plurality of configurable retimers that retime the input data where at least a portion of one of the plurality of configurable retimers is enabled based on the configured data rate.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 20, 2024
    Assignee: ETOPUS TECHNOLOGY INC.
    Inventors: Tze Yin Cheung, Paul K. Lai, Danfeng Xu
  • CONFIGURABLE TRANSMITTER DEVICE BASED ON DATA RATE
    Publication number: 20230418322
    Abstract: A transmitter device includes a configurable timer circuit that adjusts timing of input data for serial transmission of the input data. The configurable timer circuit may be configured depending on the configured data rate of the transmitter device. In one embodiment, the configurable timer circuit includes a plurality of configurable retimers that retime the input data where at least a portion of one of the plurality of configurable retimers is enabled based on the configured data rate.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Tze Yin Cheung, Paul K. Lai, Danfeng Xu
  • Clock duty cycle calibration and phase calibration for high-speed transmitter
    Patent number: 11438199
    Abstract: A transmitter device having a calibrator circuit is disclosed. The calibrator circuit performs duty cycle calibration and phase calibration on a plurality of clock signals of the transmitter device. In one embodiment, the phase calibration is performed based on a comparison of the clock signals to a reference clock signal from the plurality of clock signals. In another embodiment, the calibrator circuit uses fixed patterns of data signals to perform phase calibration on the plurality of clock signals.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: September 6, 2022
    Assignee: eTopus Technology Inc.
    Inventors: Danfeng Xu, Xiaolong Liu, Hon Man Yau, Paul K. Lai, Kai Keung Chan
  • Pad bit injection during read operation to improve format efficiency
    Patent number: 8570680
    Abstract: Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: October 29, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Kwok W. Yeung, Kai Keung Chan, Paul K. Lai
  • Low power viterbi trace back architecture
    Patent number: 8185810
    Abstract: A method of obtaining a Viterbi decoded value is disclosed. A decision output is stored to one of a plurality of buffer elements, wherein at least one other buffer element in the plurality is not changing; and data is exposed in the buffer element. A plurality of stored decision outputs is obtained from the plurality of buffers elements. The obtained plurality of stored decision outputs is processed to obtain a Viterbi decoded value.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: May 22, 2012
    Assignee: Link—A—Media Devices Corporation
    Inventors: Kwok Alfred Yeung, Xin-Ning Song, Paul K. Lai
  • PAD BIT INJECTION DURING READ OPERATION TO IMPROVE FORMAT EFFICIENCY
    Publication number: 20120019950
    Abstract: Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.
    Type: Application
    Filed: May 23, 2011
    Publication date: January 26, 2012
    Applicant: LINK_A_MEDIA DEVICES CORPORATION
    Inventors: Kwok W. Yeung, Kai Keung Chan, Paul K. Lai
  • Pad bit injection during read operation to improve format efficiency
    Patent number: 7974033
    Abstract: Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: July 5, 2011
    Assignee: Link—A—Media Devices Corporation
    Inventors: Kwok W. Yeung, Kai Keung Chan, Paul K. Lai
  • Bridge type optoelectronic sample and hold circuit
    Patent number: 5239181
    Abstract: A novel bridge type optoelectronic (OE) sample and hold circuit based upon current steering demonstrates a clear superiority in performance with respect to a direct OE sample and hold circuit. The bridge type OE sample and hold circuit permits a high-speed signal to be sampled with high accuracy to offer high charging capability, commanding signal isolation, reduced time jitter and reduced holding charge leakage which are distinct advantages over conventional electronic sample and hold circuits.
    Type: Grant
    Filed: December 31, 1990
    Date of Patent: August 24, 1993
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Chen-Kuo Sun, Chao C. Wu, Ching T. Chang, Paul K. Lai Yu, William H. McKnight