Abstract: A method to soft start a charge pump circuit according to embodiments includes enabling switching for a plurality of power transistors, selecting a first switching control signal from a plurality of switching control signals for the selected plurality of power transistors, slowly ramping up a plurality of bootstrap supply voltages associated with the selected plurality of power transistors, driving a gate-to-source voltage of each power transistor of the selected plurality of power transistors at a first predefined level, and determining if the plurality of bootstrap supply voltages are less than a second predefined level. If the plurality of bootstrap supply voltages are less than the second predefined level, the method further includes toggling and thereby selecting a second switching control signal from the plurality of switching control signals for a second selected plurality of power transistors.

Abstract: A method to soft start a charge pump circuit according to embodiments includes enabling switching for a plurality of power transistors, selecting a first switching control signal from a plurality of switching control signals for the selected plurality of power transistors, slowly ramping up a plurality of bootstrap supply voltages associated with the selected plurality of power transistors, driving a gate-to-source voltage of each power transistor of the selected plurality of power transistors at a first predefined level, and determining if the plurality of bootstrap supply voltages are less than a second predefined level. If the plurality of bootstrap supply voltages are less than the second predefined level, the method further includes toggling and thereby selecting a second switching control signal from the plurality of switching control signals for a second selected plurality of power transistors.

Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

Abstract: A multi-level current pulse generator for driving the gates of a CMOS pair implemented using a low voltage process including a multi-level pulse translator, a current amplifier circuit, and a clamp circuit. The multi-level pulse translator generates a multi-level current pulse on at least one pulse node, each current pulse having a first large current pulse with short duration followed by at least one smaller current pulse of longer duration and operative to switch the CMOS pair with reduced average power dissipation. The current amplifier circuit amplifies the current pulses provided to the gates of the CMOS pair. The clamp circuit clamps gate voltage of the CMOS pair to prevent breakdown. In a tri-level case, a first current pulse charges and discharges gate capacitance, a second current pulse stabilizes gate voltage, and a third current pulse provides a holding current level.

Abstract: A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.

Abstract: A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.

Abstract: The problem of charge leakage in the AC compensation filter for the error amplifier of a pulse width modulation (PWM)-based DC—DC converter is effectively obviated by controllably sampling and storing the voltage across the AC compensation filter, in response to a transition of the operation of a DC power supply from run or active mode to quiescent or sleep mode. The sampled voltage is retained as a compensation voltage throughout the quiescent mode, so that it will be immediately available to the PWM circuitry at the termination of the quiescent interval. This serves to ensure a relatively smooth (low noise) power supply switch-over during a subsequent transition from quiescent to active mode.

Abstract: A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC—DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

Abstract: A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

Abstract: A programmably switched, multi-output stage current mirror-based, current-sensing and correction circuit controls the operation of a buck mode DC—DC converter. This correction circuit generates a correction current having a prescribed step-wise temperature-compensating relationship to sensed current. The sensed current is derived from a variable impedance controlled by a sense amplifier coupled via a current feedback resistor to the common output node between a high side power switching device and a low side power switching device of the converter. To program the correction circuit a decoder maps temperature information associated with the low side power switching device and additional programming information into a current mirror control code.

Abstract: A programmably switched, multi-output stage current mirror-based, current-sensing and correction circuit controls the operation of a buck mode DC-DC converter. This correction circuit generates a correction current having a prescribed step-wise temperature-compensating relationship to sensed current. The sensed current is derived from a variable impedance controlled by a sense amplifier coupled via a current feedback resistor to the common output node between a high side power switching device and a low side power switching device of the converter. To program the correction circuit a decoder maps temperature information associated with the low side power switching device and additional programming information into a current mirror control code.

Abstract: A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.

Abstract: A circuit and method for synchronizing multiple transmitting devices in a multiplexed communication system in which transmitting nodes generate bit transitions on the multiplexed bus based on the time elapsed since the last received bit transition, and in which the synchronization is dependent only on the last received bit transition and on no other synchronization signal. The circuit and method may be used to prevent inadvertent bit transition transmission within a predetermined period of time of receipt of a bit transition.

Abstract: A method of generating a cyclic redundancy check (CRC) word during transmission and of validating a CRC word during reception in a multiplex data communication system using a single CRC register. A CRC word is generated as data are transmitted by calculating the CRC word based on reflected data, rather than on the transmitted data. The transmitted data is reflected back to the transmitting unit's CRC generation block and the CRC word is immediately generated and appended to the outgoing transmission. In an aspect of the invention and to check whether the transmission was error-free, the one's complement of a CRC word is generated and stored in a CRC register, and the reflected transmission of the CRC word is circulated through the CRC register to yield a predetermined constant value if the transmission was error free.

Abstract: An emulator circuit and method of emulating operation of a computer system in which the emulator circuit may be selectively operated with memory devices that require coincident availability of data and address information during a clock cycle, and with systems that require data and address information at different times during the clock cycle. (Address information including address signals for selecting memory locations and memory control signals.

Abstract: A method and device for timing bit transitions in a data communication system includes a multi-purpose counter/decoder responsive to transmission of bit transitions and receipt of reflections of the transmitted bit transitions to (a) indicate when the next bit transition is to be transmitted after a bit transition has been received during normal operation, (b) indicate a fault when a reflection of the transmitted bit transition is not received within a predetermined time count, and (c) determining the duration of a received bit.

Abstract: A method and circuit for selectively scaling a binary counter having N serially connected stages in which an output count from the counter is 2.sup.M times the number of clock signals that have been input to the counter. The first M stages of the counter are selectively held so that clock signals by-pass (or pass through) the first M stages without change. The M+1 stage receives each clock signal and is thereby caused to indicate that 2.sup.M clock signals have been received, when only one clock signal has, in fact, been received. The output of each stage is provided to a decoder array that provides the scaled count signal. The method and circuit find application in systems in which normal unscaled operation of the binary counter may be selectively replaced with high speed operation, such as during tests or during special operating modes. The circuit and method obviate the need for a separate high speed clock, or for adaptive circuitry in the decoder array.