Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract: Apparatus and methods of de-convolution for multi-phase scans of an array of electrodes are described. One programmable circuit includes a sequencer to initiate a multi-phase transmit (TX) scan of an array of electrodes to obtain capacitance data. The capacitance data is stored in one or more storage devices as convoluted capacitance data. The programmable circuit also includes a digital circuit block to read the convoluted capacitance data from the one or more storage devices, de-convolve the convoluted capacitance data to obtain de-convoluted capacitance data, and store the de-convoluted capacitance data in the one or more storage devices.

Abstract: An embodiment of a method for detecting noise for a capacitance sensing panel may comprise generating an input signal based on a noise signal, performing a series of measurements for measuring capacitances from a capacitive sensor sensitive to the noise signal, and controlling timing for at least one of the subconversions based on the input signal.

Abstract: Apparatus and methods of de-convolution for multi-phase scans of an array of electrodes are described. One programmable circuit includes a sequencer to initiate a multi-phase transmit (TX) scan of an array of electrodes to obtain capacitance data. The capacitance data is stored in one or more storage devices as convoluted capacitance data. The programmable circuit also includes a digital circuit block to read the convoluted capacitance data from the one or more storage devices, de-convolve the convoluted capacitance data to obtain de-convoluted capacitance data, and store the de-convoluted capacitance data in the or more storage devices.

Abstract: An embodiment of a method for detecting noise for a capacitance sensing panel may comprise generating an input signal based on a noise signal, performing a series of measurements for measuring capacitances from a capacitive sensor sensitive to the noise signal, and controlling timing for at least one of the subconversions based on the input signal.

Abstract: The present disclosure is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, as the generation of beat frequencies.

Abstract: An apparatus comprises a number of sub-systems and a control interface operably coupled to sub-systems for routing data therebetween. A strobe generation function is operably coupled to the control interface and configured to generate a plurality of different strobe signals to differentiate between different intended receiving devices. Thus, different strobe signals may be multiplexed onto a single control interface link, based on a pulse width or voltage magnitude characteristics of the respective strobe signals. A strobe decoder function is operably coupled to the control interface and configured to decode a plurality of different strobe signals to differentiate between triggering sub-systems on receiving devices.

Abstract: A system and method for synchronization of touch-panel devices is described. In one embodiment, the system includes a first controller device configured to control operations of a first portion of a touch-panel device such that the first controller device is further configured to generate a single master timing signal. The single master timing signal is configured to synchronize operation of the first controller device and a second controller device that is configured to control operations of a second portion of a touch-panel device.

Abstract: A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Abstract: Apparatuses and methods of hardware de-convolution for multi-phase scanning of a touch arrays are described. One apparatus includes a memory device configured to store a capacitance map including convolved capacitance data. The convolved data are results of multi-phase transmit (TX) scanning of a sense array with multiple TX patterns. The apparatus further comprises a de-convolution circuit block coupled to the memory device. The de-convolution circuit block is configured to de-convolve the convolved capacitance data with inverses of the multiple TX patterns to obtain capacitance data for a de-convolved capacitance map.

Abstract: Apparatuses and methods of hardware de-convolution for multi-phase scanning of a touch arrays are described. One apparatus includes a memory device configured to store a capacitance map including convolved capacitance data. The convolved data are results of multi-phase transmit (TX) scanning of a sense array with multiple TX patterns. The apparatus further comprises a de-convolution circuit block coupled to the memory device. The de-convolution circuit block is configured to de-convolve the convolved capacitance data with inverses of the multiple TX patterns to obtain capacitance data for a de-convolved capacitance map.

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract: A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract: A wireless communication unit has two or more communication modes including one or more mobile phone mode, in which mobile phone mode the wireless communication unit is able to transmit or receive wireless signals via an antenna from and/or to a mobile phone network in accordance with a communication protocol. The unit includes a baseband module and a radiofrequency module. A radiofrequency interface of the baseband module is connected to the radiofrequency module, for receiving and/or transmitting baseband signals from and/or to the radiofrequency module. The radiofrequency module includes a baseband interface, for receiving and/or transmitting the baseband signals to the baseband module and an antenna interface (AI) connectable to an antenna for receiving and/or transmitting radiofrequency signals from and/or to the antenna. A clock system is connected to the radiofrequency interface and the baseband interface.

Abstract: A communication device is capable of supporting communication compliant with a Dual-Mode 2.5G and 3G interface baseband-radio frequency interface standard and comprises a data interface operably coupled to a number sub-systems and a clock circuit generating a plurality of clock phases for supporting communication there between. At least one of the number of sub-systems comprises a line driver and a line receiver; wherein the communication device is characterized in that the line receiver determines an end of a received data frame sent across the data interface and in response thereto switches itself off.

Abstract: An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.

Abstract: A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronization logic operably coupled to a counter, such that data is sampled by the timing synchronization logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterized in that the timing synchronization logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronization.

Abstract: A master radiofrequency integrated circuit (RF IC) and a slave radiofrequency integrated circuit include a master radiofrequency module and a slave radiofrequency module, respectively. Both RF ICs include a radiofrequency side contact connectable to an antenna, for receiving radiofrequency signals, via the antenna, from a wireless communications network and a baseband side contact connected to the radiofrequency module and connectable to a contact of a baseband integrated circuit, for transmitting the baseband signals from the master radiofrequency module to the baseband integrated circuit. The RF module is connected to the radiofrequency side contact, for converting the radiofrequency signals into baseband signals. The master radiofrequency module includes a slave control unit for controlling the slave radiofrequency module.

Abstract: A wireless communication unit includes a baseband module and a radiofrequency module. A communication interface connects the baseband module to the radiofrequency module. Data can be communicated from the baseband module to the radiofrequency module and/or vice versa via the interface. The communication interface includes one or more data compression arrangement, for compressing original data to be transmitted over the communication interface, from a transmitting side of the communication interface to a receiving side of the communication interface, into compressed data and decompressing the compressed data after transmission and restoring the original data. The data compression arrangement may include a data compression unit at the transmitting side of the communication interface, and a data decompression unit at the receiving side of the communication interface.