Abstract: During readout, the signals induced on the columns of a charge transfer array cause currents to flow through respective conduction paths of field effect transistors connected to the columns. The threshold voltage V.sub.th of each transistor is compensated for prior to readout by establishing the gate electrode thereof at a quiescent gate bias level V.sub.c +V.sub.th, where V.sub.c is the quiescent voltage at the source electrode of that transistor. The effects of dark current or other fixed signal level it is desired to discriminate against associated with the respective columns of the array, also may be compensated for by reducing the quiescent bias level on the gate electrode by an amount proportional thereto.

Abstract: During the integration of odd fields, alternate row conductors of a charge injection device (CID) array successively are placed at an operating potential at which charge carriers photoexcited in the substrate may be collected at the CID's along each such row. Isolation between such rows is achieved by successively placing the intervening row conductors at a potential to form potential barriers in the substrate. During the integration of even fields, the roles of the row conductors are reversed. Operation in this way results in vertical interlace and it permits the charge collecting locations of the CID array to be spaced relatively close to one another in the column direction, that is, it permits relatively high resolution in the column direction.

Abstract: The combination of an X-Y addressed array of charge injection devides (CIDs) and a charge transfer output register system. The array is read out a row at a time by first restoring charge to the columns of the array, then removing the excess charge from the columns to reset them to a reference potential, then causing the photo-induced charge carriers in a row to change the column potentials to extents dependent upon the photo-induced charge levels. This change in potential is employed to supply charge signals in parallel to the charge transfer stages of the output register system.

Abstract: During the serial shifting to an output buffer of the radiation induced charge signal accumulated in a row (or column) of an array, the successive signals are processed to improve the contrast of the sensed image. The portion of each signal of greater than a given amplitude is transmitted to a buffer stage and the remaining portion of each signal is removed. In one form of the invention, the signal-to-noise ratio is then enhanced at the expense of resolution by combining at the buffer the processed signal from a number of adjacent charge storage locations.

Abstract: The columns of a charge transfer imager are arranged in groups with N columns in each group, each column of a group receiving light through a different color filter. Upon the completion of the integration time, each line is shifted out of the imager 1/N'th of a line at a time, each N'th of a line representing a different color component of the image. The different parts of each line subsequently are read serially and concurrently to obtain the N color signal components of each resolution element of the imager.

Abstract: Charge transfer memories such as those of the bucket-brigade or of the charge-coupled device (CCD) type include, at each location, a store which is separate from the normal means for charge storage. Charge is transferred from the normal means of storage to the separate store at each location during a first period of time and may be sensed during later intervals of time to provide multiple "copies" of the stored information. In one form of such a memory especially suitable for the storage of digital data, each separate store includes an internal loop for refreshing the charge. In other forms of such memories, means are provided for reducing the effects of variation in threshold voltage from location-to-location of the transistors associated with the separate stores. These are especially suitable for analog storage.