Abstract: A self-assembled metal mesh transparent conductive film and the method of fabricating the same are provided in the present invention. Some key aspects of the present invention are as follows: 1) to control the opening size in self-assembled metal mesh transparent conductive film; 2) to tune the surface energy of substrate using surface treatment; 3) to improve transparency of metal mesh by low-temperature method such as chemical etching; 4) to increase the conductivity of metal mesh without high temperature annealing; and 5) to strengthen the metal mesh film by post-treatment. The transparent conductive film of the present invention can be formed on rigid or flexible substrates. The present method enables tuning the transparency and conductance of the metal mesh film through tuning the opening size of metal mesh, and is also cost-effective due to low process cost and high material utilization rate.

Abstract: To fabricate a perovskite solar cell (PSC), a printable carbon electrode is formed on an uppermost layer, either a perovskite layer or an interface layer thereon, of a partially-completed PSC. A carbon ink is first prepared by dispersing carbon materials in a mixture of a polymer binder and a solvent. Then the carbon ink is screen-printed on the uppermost layer to form a wet film thereon. The wet film is baked with a baking temperature not exceeding 100° C. to evaporate the solvent to form the carbon electrode. Advantageously, the wet film is pressed with a pressure during baking such that the carbon electrode becomes denser and yields a lower sheet resistance when compared to one formed without being pressed. Preferably the pressure is at least 16,000 Pa. Experimental results show that the percentage reduction of sheet resistance can reach 40%.

Abstract: The present invention relates to newly functionalized polythiophenes and the syntheses thereof. The present invention also demonstrates that the new polythiophenes and their derivatives are suitable for fabricating organic light emitting diodes (OLEDs), light emitting diodes (PLEDs), organic photovoltaic devices (OPVs) and conducting polymers for printed electronic devices.

Abstract: The present invention describes a method of producing a p-type light-absorbing semiconductor copper zinc tin selenide/sulfide (Cu2(ZnxSn2-x)(SySe1-y)4) (abbreviated CZTS) with electrochemical deposition. It can be used in the production of solar cell when combined with an n-type inorganic or an organic semiconductor layer. The present method comprises a one-step or a sequence of depositions using electroplating to fabricate a low-cost and large-area CZTS solar cell, without using expensive and complicated deposition techniques or highly toxic and flammable chemicals in the production process. The present method significantly reduces the cost and energy requirement for production of solar cell.

Abstract: The present invention relates to newly functionalized polythiophenes and the syntheses thereof. The present invention also demonstrates that the new polythiophenes and their derivatives are suitable for fabricating organic light emitting diodes (OLEDs), light emitting diodes (PLEDs), organic photovoltaic devices (OPVs) and conducting polymers for printed electronic devices.

Abstract: The present invention describes a method of producing a p-type light-absorbing semiconductor copper zinc tin selenide/sulfide (Cu2(ZnxSn2-x)(SySe1-y)4) (abbreviated CZTS) with electrochemical deposition. It can be used in the production of solar cell when combined with an n-type inorganic or an organic semiconductor layer. The present method comprises a one-step or a sequence of depositions using electroplating to fabricate a low-cost and large-area CZTS solar cell, without using expensive and complicated deposition techniques or highly toxic and flammable chemicals in the production process. The present method significantly reduces the cost and energy requirement for production of solar cell.

Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.

Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.

Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.

Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.

Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.

Abstract: A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces.

Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit.

Abstract: A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.

Abstract: A method is disclosed for removing metal from semiconductor substrates, optionally with or without the use of an abrasive slurry, and the attendant problems of defects caused by mechanical scratches, chemical corrosion and oxidation of components as is normally encountered with the well-known chemical-mechanical polishing (CMP) techniques. The metal removal is accomplished by placing a substrate having the metal layer in an electrolytic system in a tank, and rotating a pad against the substrate while passing current through the system including a cathode and the anodic metal layer. Preferably, the pad size is smaller than that of the substrate. The action of the pad against the metal layer moves an additive in the electrolytic solution from high regions to low regions on the metal layer, thus exposing the high regions to be polished away until all the regions are planarized to molecular height of the additive across the whole metal layer.

Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.