Patents by Inventor Paul L. Bereznycky
Paul L. Bereznycky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12051665Abstract: A system includes a die with a first plurality of hybridization bumps extending therefrom, electrically connected to circuitry die. An external circuitry component with a second plurality of hybridization bumps extending therefrom, electrically connected to circuitry in the external circuitry component. The first plurality of hybridization bumps and the second plurality of hybridization bumps are pressed together for electrical communication between the die and the external circuitry component. The first plurality of hybridization bumps have a different material hardness from the second plurality of hybridization bumps. The first plurality of hybridization bumps have a different bump diameter from that of the second plurality of hybridization bumps.Type: GrantFiled: March 25, 2022Date of Patent: July 30, 2024Assignee: SENSORS UNLIMITED, INC.Inventors: Wei Huang, Sungjin Kim, Paul L Bereznycky, Michael J. Evans, De Hsin Chang, Wei Zhang
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Patent number: 11923470Abstract: A method includes forming an assembly of layers including an InP cap layer on an InGaAs absorption region layer, wherein the InGaAs layer is on an n-InP layer, and wherein an underlying substrate layer underlies the n-InP layer. The method includes removing a portion of the InP cap and n-InP layer by dry etching.Type: GrantFiled: October 24, 2022Date of Patent: March 5, 2024Assignee: Sensors Unlimited, Inc.Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Paul L. Bereznycky, Sean T. Houlihan
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Publication number: 20230307398Abstract: A system includes a die with a first plurality of hybridization bumps extending therefrom, electrically connected to circuitry die. An external circuitry component with a second plurality of hybridization bumps extending therefrom, electrically connected to circuitry in the external circuitry component. The first plurality of hybridization bumps and the second plurality of hybridization bumps are pressed together for electrical communication between the die and the external circuitry component. The first plurality of hybridization bumps have a different material hardness from the second plurality of hybridization bumps. The first plurality of hybridization bumps have a different bump diameter from that of the second plurality of hybridization bumps.Type: ApplicationFiled: March 25, 2022Publication date: September 28, 2023Applicant: Sensors Unlimited, Inc.Inventors: Wei Huang, Sungjin Kim, Paul L. Bereznycky, Michael J. Evans, De Hsin Chang, Wei Zhang
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Publication number: 20230050990Abstract: A method includes forming an assembly of layers including an InP cap layer on an InGaAs absorption region layer, wherein the InGaAs layer is on an n-InP layer, and wherein an underlying substrate layer underlies the n-InP layer. The method includes removing a portion of the InP cap and n-InP layer by dry etching.Type: ApplicationFiled: October 24, 2022Publication date: February 16, 2023Applicant: Sensors Unlimited, Inc.Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Paul L. Bereznycky, Sean T. Houlihan
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Publication number: 20210104638Abstract: A method includes forming an assembly of layers including an InP cap layer on an InGaAs absorption region layer, wherein the InGaAs layer is on an n-InP layer, and wherein an underlying substrate layer underlies the n-InP layer. The method includes removing a portion of the InP cap and n-InP layer by dry etching.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Applicant: Sensors Unlimited, Inc.Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Paul L. Bereznycky, Sean T. Houlihan
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Patent number: 10957733Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.Type: GrantFiled: June 16, 2020Date of Patent: March 23, 2021Assignee: Sensors Unlimited, Inc.Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Wei Huang, Paul L. Bereznycky, Namwoong Paik
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Publication number: 20200312900Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Applicant: Sensors Unlimited, Inc.Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Wei Huang, Paul L. Bereznycky, Namwoong Paik
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Patent number: 10727267Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.Type: GrantFiled: September 12, 2018Date of Patent: July 28, 2020Assignee: Sensors Unlimited, Inc.Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Wei Huang, Paul L. Bereznycky, Namwoong Paik
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Publication number: 20200083272Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.Type: ApplicationFiled: September 12, 2018Publication date: March 12, 2020Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Wei Huang, Paul L. Bereznycky, Namwoong Paik
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Publication number: 20200052012Abstract: A method of forming an array of photodiodes includes forming a cap layer on a surface of an absorption layer. The method includes forming a plurality of spaced apart pixel diffusion areas in the cap layer. The method includes forming a mesa trench with opposed sidewalls through the cap layer, wherein the mesa trench surrounds each of the pixel diffusion areas separating the pixel diffusion areas from one another. The method includes forming a sidewall passivation layer over the sidewalls of the mesa trench and removing a portion of the sidewall passivation layer to expose a respective contact electrically connected to each of the pixel diffusion areas, but leaving the sidewalls of the mesa trench covered with the sidewall passivation layer wherein the contact is open and uncovered for electrical connection.Type: ApplicationFiled: August 7, 2018Publication date: February 13, 2020Inventors: Wei Zhang, Michael J. Evans, Douglas Stewart Malchow, Paul L. Bereznycky, Namwoong Paik