Abstract: An apparatus and method for supplying an address and data to an external memory device. The number of pins available for supplying the address is less than the number of address lines required at the external memory device. A register is used to store the high order bits of the address and is pre-loaded with a default page value. An output of the register is coupled to an address input of the external memory. If the high order bits of the address are equal to the default page value, a control device couples the data lines directly to the external memory device and a read or write operation follows. If the two values are different, a paging cycle is performed where the high order address bits are latched through the register to the address input of the external memory and then the data bits are coupled to the external memory device.

Abstract: A method and apparatus for improving the performance of the transferring of transaction handshakes between sections of synchronous logic which are in different timing domains providing immunity from set-up and hold violations and associated problems of metastability, by reducing the time overhead required for signal synchronization.

Abstract: A bus interface coupling one or more processors to a standardized bus, such as the Futurebus. The bus interface controls the assertion of all address and data handshaking signals on the bus while sending control signals to address/data transceivers coupled in between the bus and the processors. The interface comprises a plurality of synchronous state machines coupled to the processors for passing status and command data to a plurality of master and slave devices coupled to the bus. The interface also comprises a plurality of asynchronous state machines coupled between the synchronous state machines and the bus. The asynchronous machines quickly detect and assert the necessary handshaking signals of the bus protocol. The interface also controls the address/data transceivers coupled between the processors and the bus and provides an efficient throughput of data to and from the bus. Items coupled to the bus interface can operate either as slave or master devices.