Abstract: A fringe capacitor with a shielded the top capacitor plate is formed in multiple interconnect layers to include a first plate having a first defined finger structure located in one or more middle interconnect layers to form a top capacitor plate; a set of second plates located in the middle interconnect layer(s) and bottom and top interconnect layers that are connected to form a bottom capacitor plate which includes a second plate in the middle interconnect layer(s) having defined finger structures that are interleaved with the first defined finger structure of the top capacitor plate to vertically and horizontally sandwich the top capacitor plate; and a set of shield layers formed to surround and shield the top capacitor plate on lateral sides, where the set of shield layers are connected to a reference voltage, thereby shielding the top capacitor plate from parasitic capacitance.

Abstract: A fringe capacitor with a shielded the top capacitor plate is formed in multiple interconnect layers to include a first plate having a first defined finger structure located in one or more middle interconnect layers to form a top capacitor plate; a set of second plates located in the middle interconnect layer(s) and bottom and top interconnect layers that are connected to form a bottom capacitor plate which includes a second plate in the middle interconnect layer(s) having defined finger structures that are interleaved with the first defined finger structure of the top capacitor plate to vertically and horizontally sandwich the top capacitor plate; and a set of shield layers formed to surround and shield the top capacitor plate on lateral sides, where the set of shield layers are connected to a reference voltage, thereby shielding the top capacitor plate from parasitic capacitance.