Abstract: Disclosed are control systems, and more specifically control systems which benefit from a long-gate time for measurement and a rapid sample time to enhance responsiveness and methods and systems for utilizing multiple-staggered, overlapping gates where the gate time is an integer multiple of the time between ends of adjacent gates. The system continuously counts at the wavefronts or zero-crossings of a frequency reference signal and temporarily records them in registers and compares the contents of registers separated by a gate time and outputs a sample after every sample time.

Abstract: A frequency synthesizer has a fractional N1 loop and an integer N2 loop. The output frequency of the signal of the fractional N1 loop is constrained to values between adjacent harmonics of a reference frequency used in the fractional N1 loop. The signal of the fractional N1 loop is received by the integer N2 loop. The integer N2 loop provides an output signal. The output signal can be a high frequency signal such as 2-8 GHz signal.

Abstract: A polynomial expansion of the z-transform characterization of an n'th order differentiator component's output is utilized to implement a differentiator having reduced gates. The differentiator component comprises at least one adder and a plurality of latches, both having inputs and outputs. The connection of the inputs and outputs is dependent on a polynomial expansion of the z-transform characterization of the differentiator components output. A method of reducing gates in an Nth order differentiator component includes characterizing the differentiator component's output by a z-transform. A polynomial expansion of the z-transform characterization is used to implement a differentiator. A differentiator that is implemented based on a polynomial expansion utilizes fewer gates to achieve the same mathematical function.

Abstract: A phase detector with a linear gain characteristic includes two exclusive-OR gates with inputs connected to an input signal and an inverted input signal and a reference signal in a phase locked loop. The outputs of the exclusive-OR gates are connected to a plurality of switches. The switches are connected to a plurality of resistors and the resistors are connected together to form an output signal. Switches and resistors are selected in complementary pairs by a gain select function to provide a linear gain characteristic for the output signal.

Abstract: A method to reduce latency in an n'th order differentiator and in a frequency synthesizer having a MASH structure of sigma-delta modulators includes characterizing the differentiator according to its z-transform transfer function. The transfer function polynomial is expanded using Horner's Rule. Realizing the expanded polynomial in hardware reduces latency in both the differentiator and the frequency synthesizer. An n'th order differentiator utilizes parallel inputs in adders and latches and implicit multiplication at adder inputs to realize the z-transform transfer function using Horner's Rule. An n'th order MASH structure of sigma-delta modulators has n'th differentiators, each differentiator implementing a z-transform polynomial transfer function expanded using Horner's Rule.

Abstract: A programmable prescaler for scaling an input frequency into a desired output frequency including an input divider having an input connected to the input frequency and a divided output, a first counter, having an input connected to the divided output of the input divider and a terminal count output; and a second counter coupled to the terminal count output of the first counter having a scaled-frequency output. The second counter may be a divide by two counter, and may be coupled to the terminal count output of the first counter via the input divider. The input divider further may further include a plurality of divider stages, the input frequency and the terminal count output being cascaded through the plurality of divider stages, and wherein the second counter is coupled to the terminal count output of the first counter via the plurality of divider stages of the input divider.

Abstract: A method and apparatus are provided for modulating a frequency synthesizer with an adjusted frequency control word determined by adjusting a carrier frequency control word based upon a bit content of a unsigned modulation control word. The method includes the steps of inverting a most significant bit of the unsigned modulation control word to produce an adjusted modulation control word and replicating the inverted most significant bit and appending the replicated bits to a most significant bit side of the adjusted modulation control word to increase a width of the adjusted modulation control word to a width of the carrier frequency control word. The method further includes the step of adjusting the carrier frequency control word by adding the replicated bits and the adjusted modulation control word to corresponding bits of the carrier frequency control word.

Abstract: A phase-locked loop frequency synthesizer system is provided using fractional frequency division and a fractional control number for phase modulating an output of the frequency synthesizer using an incoming information signal. The apparatus includes a delta-sigma converter which adjusts a divisor of the frequency divider by operating upon a magnitude modulated fractional frequency control number. The system further includes a differentiator which provides the magnitude modulated input stream to the delta-sigma modulator by modulating the fractional control number with detected differences in the incoming information signal.