Abstract: Disclosed herein is a technique to transfer at least one unfinished operation from one controller to a second controller, if the first controller has ceased.

Abstract: A method of manufacturing a computing apparatus may include providing a plurality of computer components for the computing apparatus. The computing apparatus and the plurality of computer components can be transported from an origin to a geographically distant destination with a transport vehicle. Manufacture of the computing apparatus is substantially completed during the transporting of the computing apparatus.

Abstract: Embodiments include a server and a sensor that detects when a first fluid line to the server fails so a second fluid line to the server is activated.

Abstract: A noise suppression circuit is presented which improves signal quality on signal control lines of dynamic logic circuits. The noise suppression circuit provides dynamic line termination and immunity to cross-coupling of signals from other control lines. The line termination portion of the circuit suppresses high-transitioning pulses on low-drive control lines by referencing the low control line level to the local ground and low-transitioning pulses on high-drive control lines by referencing the control line level to a local power supply to immunize pass-gate logic. The input of a CMOS inverter is coupled to the control line. The drain of a FET is coupled to the output control line, and its gate is coupled to the output of the CMOS inverter. Suppression of high-transitioning and low-transitioning pulses is achieved by coupling the source of the FET to the local ground or local power supply respectively.

Abstract: A method and apparatus for improving the forward path switching speed of a complementary CMOS inverter is presented. A large P-type to N-type FET ratio is used to tune the inverter trigger point to the falling edge of the input signal to the inverter. The high P-type to N-type ratio is made feasible by adding a precharge assist pull-down transistor in parallel on the output node of the inverter.

Abstract: Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information.

Abstract: An evaluation phase expansion system for increasing the operating frequency of a dynamic logic circuit which includes a plurality of logic stages. The plurality of logic stages are partitioned into a first set of logic stages which are responsive to an early clock signal and which evaluate in an early evaluate phase and a second set of logic stages which are responsive to a late clock signal and which evaluate in a late evaluate phase. The late evaluate phase of the late clock signal commences during the early evaluate phase of the early clock signal and terminates during an early pre-charge phase of the early clock signal in order to artificially induce clock asymmetry to compensate for logic asymmetry in alternating pipeline phases of the dynamic logic circuit.

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements.

Abstract: A single-phase clocking scheme for use in a VLSI chip having a plurality of localized logic blocks implemented thereon is presented. The present invention includes a first level global clock buffer for receiving an external global clock and producing a first level global clock. A plurality of second level clock buffers, one corresponding to each localized logic block, receive the first level global clock via protected equal length lines, and each produce a respective second level global clock. Each of the localized logic blocks include a plurality of third level clock buffers, wherein each third level clock buffer receives the second level global clock of its respective localized logic block, and each produces a third level local clock. The third level local clock buffers within each localized logic block generate different clocking schemes from each of the other third level local clock buffers contained within the same localized block.

Abstract: Disclosed herein are methods and apparatus for performing magnitude comparisons within a shift-merge unit (SMU). A programmable or partially programmable Manchester carry chain is used to perform each comparison. The Manchester carry chains are programmed using the bits of mask markers and are constructed so as to make a comparison with respect to a given mask condition and position marker which are constants. An implementation in dual rail dynamic CMOS logic avoids the necessity of input inversions, and allows construction of more compact Manchester carry chain circuitry. The size of an SMU will therefore be determined by mask marker routings rather than transistor count. When shorted, opened, and/or redundant transistors, and/or transistors programmed with constants are optimized out of constructed Manchester carry chains, the mask marker bits of a dual rail SMU will have equal fanouts, thereby preventing clock skew.