Abstract: A photosensitizer formulation can be disposed on or in a mesh; net; netting; screen; curtain of strands, fibers, or monofilaments; substrate, personal protective gear, mask, or any other suitable object. The photosensitizer formulation, when in contact with molecular oxygen and activated by light or ultrasound, produces microbicidal singlet oxygen. A variety of different arrangements and applications are described. For example, an air flow device may also be included to generate a flow of air through or over the photosensitizer formulation. A fluorescent formulation may be included to monitor photobleaching. The photosensitizer formulation may be disposed in a concentration gradient to generate antigenic particles by damaging or destroying microbes.

Abstract: A tri-barrier ceramic coating system is provided having a base thermal barrier layer, an intermediate CMAS barrier layer, and a top erosion barrier layer, and the method of applying such a coating system to a substrate. The base layer has a typical columnar structure with inter-columnar gaps and intra-columnar micro-pores that provides the stress tolerance during thermal cycles. The intermediate CMAS barrier layer has the fiber-like columns with inter-columnar nano-pores and a grid structure on the bottom of the layer. The fine structured intermediate layer covers the gaps between the columns of the base layer and will block CMAS infiltration effectively. The top erosion resistant layer contains wider TBC columns with narrow inter-columnar gaps and a modified cauliflower-like TBC head that provides erosion resistance for the underlying layers. The tri-barrier coating microstructure will further reduce the thermal conductivity as comparing to the conventional single layer system.

Abstract: Selective trace cache invalidation for self-modifying code via memory aging advantageously retains some of the entries in a trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. Associated with each trace cache entry are translation ages that are determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein processed, the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented. If one of the current ages overflows, then the entire trace cache is flushed.

Abstract: A trace cache for efficient self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. Associated with trace cache entries are one or more translation ages, determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein are processed, each of the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented.

Abstract: Efficient trace cache management during self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. One or more translation ages are associated with each trace cache entry, and are determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein are processed, the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented.

Abstract: This invention provides a thermal barrier ceramic coating for application to a metallic article, with the ceramic coating having a formula of NdxZr1-xOy with Z dissolved in, where 0<x<0.5 and 1.75<y<2 and wherein Z is an oxide of a metal selected from the group consisting of Y, Mg, Ca, Hf and mixtures thereof. In one embodiment Nd is added at a level up to 7 mole %. In another embodiment Z is yttrium and is added at a level of at least 6 wt %.

Abstract: This invention provides a thermal barrier ceramic coating for application to a metallic article, with the ceramic coating having a formula of RexZr1-xOy with Z dissolved in wherein Re is a rare earth element selected from the group consisting of Ce, Pr, Nd, Pm, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb and Lu, where 0<x<0.5 and 1.75<y<2 and wherein Z is an oxide of a metal selected from the group consisting of Y, Mg, Ca, Hf and mixtures thereof. A preferred embodiment is wherein Re is Nd and Z is yttrium oxide.

Abstract: This invention provides a thermal barrier ceramic coating for application to a metallic article, with the ceramic coating having a formula of NdxZr1?xOy with Z dissolved in, where 0<x <0.5 and 1.75<y<2 and wherein Z is an oxide of a metal selected from the group consisting of Y, Mg, Ca, Hf and mixtures thereof. In one embodiment Nd is added at a level up to 7 mole %. In another embodiment Z is yttrium and is added at a level of at least 6 wt %.

Abstract: This invention provides a thermal barrier ceramic coating for application to a metallic article, with the ceramic coating having a formula of RexZr1−xOy wherein Re is a rare earth element selected from the group consisting of Ce, Pr, Nd, Pm, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb and Lu where O<X<0.5 and 1.75<Y<2. A preferred embodiment is wherein Re is Nd.

Abstract: This invention provides a thermal barrier ceramic coating for application to a metallic article, with the ceramic coating having a formula of RexZr1-xOy wherein Re is a rare earth element selected from the group consisting of Ce, Pr, Nd, Pm, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb and Lu where O<X<0.5 and 1.75<Y<2. A preferred embodiment is wherein Re is Nd.

Abstract: This invention provides a metallic article with a metallic substrate having a thermal barrier ceramic coating on its surface, the ceramic coating comprising a plurality of first layers of about 6 to 8 wt % yttria stabilized zirconia alternating with a plurality of second layers of about 18 to 22 wt % yttria stabilized zirconia. The alternating layers can be distinct layers or gradient layers.