Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Abstract: Techniques are disclosed relating to reducing noise in geophysical marine survey data. Such techniques may include adapting an initial set of noise templates to recorded seismic data to generate adapted noise templates and estimating a noise component in the recorded seismic data. The estimating may include determining a degree to which noise and signal components are correlated in the recorded seismic data and masking the recorded seismic data proportionally to the degree of correlation. The adapted noise templates may then be further adapted to a difference between the estimate of the noise component and the noise templates themselves. Resultant noise templates may then be applied to denoise the recorded seismic data.

Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Abstract: A method for correction of a sea surface state can include receiving geophysical data from a seismic survey, wherein the seismic survey utilizes a plurality of receivers disposed in a body of water and at least one source in the body of water, actuated at a plurality of shot points. The method can include identifying, in the geophysical data, a wavefield based on the actuation of the at least one source, and determining, based on the identified wavefield, a sea surface state at the at least one source at one of the plurality of shot points.

Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Abstract: Techniques are disclosed relating to reducing noise in geophysical marine survey data. Such techniques may include adapting an initial set of noise templates to recorded seismic data to generate adapted noise templates and estimating a noise component in the recorded seismic data. The estimating may include determining a degree to which noise and signal components are correlated in the recorded seismic data and masking the recorded seismic data proportionally to the degree of correlation. The adapted noise templates may then be further adapted to a difference between the estimate of the noise component and the noise templates themselves. Resultant noise templates may then be applied to denoise the recorded seismic data.

Abstract: Fast anisotropy axis values are determined for each bin in seismic data binned by azimuth. A fast azimuth gather is determined within each bin in the seismic data from the fast anisotropy axis values. The earth's subsurface is imaged, using the fast azimuth gathers.

Abstract: Methods and apparatus for noise removal from seismic data. In one embodiment, a seismic data set comprising a plurality of traces is received, and noise metrics for the seismic data set are computed using a set of time and depth windows. The seismic data set is scanned to determine a first set of groups. Each group in the first set comprises at least a first minimum number of neighboring traces for which at least one of the noise metrics is outside a predefined specification. Noise attenuation is applied to the traces in the first set of groups. Other embodiments, aspects, and features are also disclosed.

Abstract: A method for correction of a sea surface state can include receiving geophysical data from a seismic survey, wherein the seismic survey utilizes a plurality of receivers disposed in a body of water and at least one source in the body of water, actuated at a plurality of shot points. The method can include identifying, in the geophysical data, a wavefield based on the actuation of the at least one source, and determining, based on the identified wavefield, a sea surface state at the at least one source at one of the plurality of shot points.

Abstract: Computational methods and systems for monitoring a petroleum reservoir are disclosed. A baseline survey is used to generate baseline data for a petroleum reservoir. Subsequent monitor surveys generate monitor data at different stages of production on the reservoir. The baseline data is reconstructed as if it was acquired at the locations of the sources and receivers of the monitor surveys, and the monitor data is reconstructed as if it was acquired at the same locations of the sources and receivers of the baseline survey. For each monitor survey, two four-dimensional (“4D”) difference data sets are generated from the baseline and monitor data and from the reconstructed data. The 4D difference data sets are combined to reduce background and produce 4D signal data that provides reliable and accurate interpretation of production activity on the reservoir.

Abstract: Disclosed are methods and apparatus for noise removal from seismic data. In one embodiment, a seismic data set comprising a plurality of traces is received, and noise metrics for the seismic data set are computed using a set of time and depth windows. The seismic data set is scanned to determine a first set of groups. Each group in the first set comprises at least a first minimum number of neighboring traces for which at least one of the noise metrics is outside a predefined specification. Noise attenuation is applied to the traces in the first set of groups. Other embodiments, aspects, and features are also disclosed.

Abstract: Fast anisotropy axis values are determined for each bin in seismic data binned by azimuth. A fast azimuth gather is determined within each bin in the seismic data from the fast anisotropy axis values. The earth's subsurface is imaged, using the fast azimuth gathers.

Abstract: A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

Abstract: The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol.

Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Abstract: In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.