Abstract: An instruction to disable a first cryptographic key of a computing device is received by a processor of the device. The first cryptographic key is embedded in the device during manufacturing to facilitate a boot sequence of the device. The instruction is signed using a cryptographic signature. The first cryptographic key is associated with a first priority indicator. The cryptographic signature is verified using a second cryptographic key embedded in the device during manufacturing. The second cryptographic key is associated with a second priority indicator. The first priority indicator is compared with the second priority indicator. Responsive to determining that the second priority indicator supersedes the first priority indicator, the first cryptographic key is disabled.

Abstract: Embodiments of the present invention provide systems and methods to enable secure communication between a host processor and external real time counter (RTC) logic. In an embodiment, the host processor generates a message including a command to an external device containing the RTC. The external device verifies a Message Authentication Code (MAC) included in the message and responds to the command. Embodiments of the present invention advantageously provide a dedicated power domain for the external RTC logic while guarding against third party attacks on the RTC logic and the communication between the RTC logic and the host processor.