Abstract: Methods and systems for processing video data are provided herein and may comprise receiving an input encoded bitstream to be processed. A portion of the received input encoded bitstream may be matched against stored indexed variable length code entries having a corresponding video information entry. If a match is found, the matched portion may be removed from the input encoded bitstream. The matching and/or the removing may be offloaded to at least one on-chip coprocessor. The coprocessor may comprise a table look-up (TLU) module with a plurality of on-chip memories, such as RAM, and may be adapted to store one or more entries from a VLC encoding/decoding table. For example, an on-chip memory may be utilized to store a VLC code entry and another on-chip memory may be utilized to store the corresponding VLC code entry attributes that each code may represent, such as LAST, RUN, and LEVEL entries.

Abstract: Methods and systems for processing video data are provided herein. Aspects of the method may comprise receiving on a chip, a plurality of video frames and storing a portion of the received video frames in a memory on the chip. A first portion of the stored video frames may be decoded on the chip and a second portion of the stored video frames may be encoded on the chip during the decoding. A third portion of the stored video frames may be converted from an input video format to a YUV video format. A reference frame corresponding to the converted third portion may be identified from the stored video frames. After conversion, the converted third portion of the received video frames may be utilized as the reference frame for estimating/encoding, or compensating/decoding temporal motion of the subsequently received video frames.

Abstract: Methods and systems for processing video data are provided herein and may comprise receiving input video information to be processed and matching a portion of the received input video information against a portion of stored indexed video information entries having a corresponding variable length code whose length varies among stored indexed video information entries. An output encoded bitstream may be generated utilizing a portion of the variable length code corresponding to the matched portion of the indexed video information to be processed. The indexed video information entries may be stored in a content addressable memory (CAM). Each bit of the indexed video information entries may be stored utilizing a content bit and/or a “don't care” indicator bit.

Abstract: Methods and systems for processing video data are disclosed herein and may comprise offloading motion estimation, motion separation, and motion compensation macroblock functions from a central processor to at least one on-chip processor for processing. For a current macroblock, reference video information may be generated via the on-chip processor by determining sum absolute difference between at least a portion of the current macroblock and at least a portion of a current search area comprising a plurality of macroblocks. Stored at least a portion of the current macroblock and/or the current search area may be received from an external memory and/or from an internal memory integrated with the on-chip processor. The sum absolute difference may be determined based on pixel luminance information corresponding to at least a portion of the current macroblock and at least a portion of the current search area.

Abstract: A method and system for ensuring data integrity in a data processing system may comprise monitoring when data for a specified device is available for error correction code generation, and receiving a first indication of the specified device, a second indication of the data, and a third indication of a size of the data during the monitoring. A new error correction code may be generated in hardware for the data based on the indicated size of the data and an indication may be provided to signal when generation of the new error correction code for a specified number of accesses for at least a portion of the data is complete. Detected errors may be corrected in software based on the newly generated error correction code. The first indication may be a device selection signal and the error correction code generation may be enabled or disabled via an enable signal.

Abstract: Distributing clock signals within an electronic device may comprise determining a status of at least one gate that controls flow of a clock signal to at least one device coupled to the gate. One or more of the gates may be controlled based on this determined status and it may be determined whether the devices coupled to the gate are active or inactive. One or more gates that control the flow of the clock signal to the device may be turned OFF if the device is inactive. The status of one or more of the gates may be read from one or more registers mapped to the gates. One or more gates that control one or more active devices may be prevented from being deactivated based on the determined status of the gates. A current hardware setting of a gate may be overridden via software control.

Abstract: Reducing power while in standby mode may comprise monitoring for an occurrence of at least one event requiring a transition out of a standby mode while utilizing a lower frequency, less accurate, and low power standby clock signal while operating in the standby mode. After receiving the occurrence of the event, an identity of the received event may be determined. In response to receiving the event, based on the determined identity of the event, a first and/or a second clock signal may be enabled, which has higher frequency and better accuracy and consumes more power than the standby clock signal. If the first and/or second clock signal is enabled, they may be disabled in order to re-enter the standby mode, which utilizes the standby clock signal while in standby mode.