Abstract: This application relates to methods and apparatus for driving a transducer. A transducer driver has a switch network is operable to selectively connect a driver output to any of a first set of at least three different switching voltages. which are, in use, maintained throughout a switching cycle of the driver apparatus. The switch network is also operable to selectively connect the driver output to flying capacitor driver. A controller is configured to control the switch network and flying capacitor driver to generate a drive signal at the driver output based on an input signal, wherein in one mode of operation the driver output is switched between two of the first set of switching voltages with a controlled duty cycle and in another mode of operation the driver output is connected to the flying capacitor driver which is switched between first and second states with a controlled duty cycle.

Abstract: A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

Abstract: A video scaling technique includes scaling a first dimension and a second dimension of a frame of video data to generate a scaled frame of video data. The scaling includes scaling the second dimension of a first portion of a frame of video data at a first rate to generate first scaled pixels and scaling the second dimension of a second portion of the frame of video data at the first rate to generate second scaled pixels. The scaling includes combining first output pixels based on the first scaled pixels and second output pixels based on the second scaled pixels to provide pixels of the scaled frame of video data at a second rate. The first rate is a fraction of the second rate.

Abstract: A video scaling technique includes scaling a first dimension and a second dimension of a frame of video data to generate a scaled frame of video data. The scaling includes scaling the second dimension of a first portion of a frame of video data at a first rate to generate first scaled pixels and scaling the second dimension of a second portion of the frame of video data at the first rate to generate second scaled pixels. The scaling includes combining first output pixels based on the first scaled pixels and second output pixels based on the second scaled pixels to provide pixels of the scaled frame of video data at a second rate. The first rate is a fraction of the second rate.

Abstract: A video processor includes a video stream translation module configured to generate a translated luminance value for a pixel of a current frame of a video data stream. The translated luminance value is based on a first luminance value for the pixel and a first translation matrix for the current frame of the video data stream. The video processor includes a filter configured to generate an output luminance value for the pixel based on the translated luminance value and a target translated luminance value for the pixel. The output luminance value may be based on a weighted average of the translated luminance value and the target translated luminance value using a first weighting factor. The video processor may include a first weighting factor generator configured to generate the first weighting factor based on luminance values of the current frame of the video stream.

Abstract: A first video picture is translated based upon a first translation matrix to adjust a contrast of the first video image. A second translation matrix is determined based upon a first histogram of a second video picture. A third translation matrix is determined based upon the first translation matrix and the second translation matrix, and the video picture is translated based upon the third translation matrix. The translation matrix can be determined using a histogram that has been adjusted using a clipped histogram equalization technique.

Abstract: A video processor includes a video stream translation module configured to generate a translated luminance value for a pixel of a current frame of a video data stream. The translated luminance value is based on a first luminance value for the pixel and a first translation matrix for the current frame of the video data stream. The video processor includes a filter configured to generate an output luminance value for the pixel based on the translated luminance value and a target translated luminance value for the pixel. The output luminance value may be based on a weighted average of the translated luminance value and the target translated luminance value using a first weighting factor. The video processor may include a first weighting factor generator configured to generate the first weighting factor based on luminance values of the current frame of the video stream.

Abstract: A first video picture is translated based upon a first translation matrix to adjust a contrast of the first video image. A second translation matrix is determined based upon a first histogram of a second video picture. A third translation matrix is determined based upon the first translation matrix and the second translation matrix, and the video picture is translated based upon the third translation matrix. The translation matrix can be determined using a histogram that has been adjusted using a clipped histogram equalization technique.

Abstract: A method and apparatus for synchronized channel transmission are disclosed.

Abstract: A first direct current (DC) component of a first amplified representation of a received signal at an output of an amplifier set to a first gain setting is determined during a first expected idle period of a received signal. A second DC component of a second amplified representation of the received signal at the output of the amplifier set to the first gain setting is determined during a second expected idle period of the received signal. A first average DC component is determined based at least in part on the first and second DC components and a DC offset used by the amplifier when set to the first gain setting is adjusted based on a comparison of the first average DC component to one or more threshold values.

Abstract: A method and apparatus for adjusting symbol timing and/or symbol interval range of a receive burst of data within a radio receiver include processing that begins by receiving a radio frequency signal that includes bursts of data. The process then continues by determining a frequency offset for the burst of data based on a difference between the transmitter processing rate and a receiver processing rate. The processing then continues by determining a symbol timing offset and/or a symbol interval range offset based on the frequency offset. The process then proceeds by adjusting the initial symbol positioning and/or the symbol interval range offset of a burst of data based on the symbol timing offset.

Abstract: A system and method for communicating with a plurality of devices are disclosed. One embodiment of the method includes transmitting a first plurality of sets of data on a plurality of data channels to a plurality of devices, wherein each of the first plurality of sets of data has a corresponding channel from the plurality of data channels and is transmitted to a corresponding device of the plurality of devices, and receiving a second plurality of sets of data on at least one of the plurality of data channels, wherein the second plurality of sets of data is sent by the plurality of devices, and wherein each of the second plurality of sets of data has a corresponding device of the plurality of devices. The second plurality of sets of data can include an acknowledgement from its corresponding device of the reception of at least one of the first plurality of data sets. Further, different channels of the plurality of data channels can include separate bands of frequencies.

Abstract: A method and apparatus for synchronized channel transmission are disclosed.

Abstract: A method and apparatus for adjusting symbol timing and/or symbol interval range of a receive burst of data within a radio receiver include processing that begins by receiving a radio frequency signal that includes bursts of data. The process then continues by determining a frequency offset for the burst of data based on a difference between the transmitter processing rate and a receiver processing rate The processing then continues by determining a symbol timing offset and/or a symbol interval range offset based on the frequency offset. The process then proceeds by adjusting the initial symbol positioning and/or the symbol interval range offset of a burst of data based on the symbol timing offset.

Abstract: A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.

Abstract: An integrated circuit that provides multiple communication functions is accomplished by providing an integrated circuit (24) that includes memory (70) which stores an audio code algorithm, echo cancellation information, a modem processing algorithm, and audio data. The memory (70) is coupled via a data bus (50) to a signal converter (56), a central processing unit (58), and a first co-processor (72). The signal converter (56) provides an analog-to-digital input port (78) and a digital-to-analog output port (80) for the integrated circuit (24), wherein the audio data is received via the analog-to-digital input port (78). The central processing unit (58) executes at least a first portion of the audio coding algorithm upon the audio data and executes a first portion of the modem processing algorithm, while the first co-processor (72) executes an echo cancellation algorithm.