Abstract: The present invention describes a robust register circuit for protecting critical control points in data transmission and telecommunications equipment against software included failures. A circuit is provided wherein duplicated data words are written into a pair of registers of any desired bit length. A digital comparator determines whether the two data words are the same, and initiates a data transfer into a third register for transmission to critical hardware control points only when two identical sequential data words are recognized. When no such recognition occurs, new data is not transferred to the third register, and the hardware control points remain controlled by the previous data in the third register.

Abstract: A frequency multiplier is disclosed for producing an output signal having a frequency greater than the frequency of an input signal by a factor (1+N/M). The frequency multiplier comprises an input terminal and an output terminal; and a plurality of frequency multiplying stages, coupled between the input and output terminals, each producing an output signal having a frequency greater than the frequency of its input signal by a factor having the general form (1+1/P).