Patents by Inventor Paul M. Chiang

Paul M. Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Storage array circuits and methods for computational memory cells
    Patent number: 11227653
    Abstract: A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 18, 2022
    Assignee: GSI Technology, inc.
    Inventors: Lee-Lean Shu, Park Soon-Kyu, Paul M. Chiang
  • Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features
    Patent number: 10192592
    Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: January 29, 2019
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Paul M. Chiang, Soon-Kyu Park, Gi-Won Cha
  • Systems and Methods Involving Data Bus Inversion Memory Circuitry, Configuration and/or Operation Including Data Signals Grouped Into 10 Bits and/or Other Features
    Publication number: 20160293231
    Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 6, 2016
    Inventors: Lee-Lean SHU, Paul M. CHIANG, Soon-Kyu PARK, Gi-Won CHA
  • Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features
    Patent number: 9384822
    Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 5, 2016
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Paul M. Chiang, Soon-Kyu Park, Gi-Won Cha
  • SYSTEMS AND METHODS INVOLVING DATA BUS INVERSION MEMORY CIRCUITRY, CONFIGURATION AND/OR OPERATION INCLUDING DATA SIGNALS GROUPED INTO 10 BITS AND/OR OTHER FEATURES
    Publication number: 20140289460
    Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 25, 2014
    Applicant: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean SHU, Paul M. Chiang, Soon-Kyu PARK, Gi-Won CHA