Abstract: Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.

Abstract: Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.

Abstract: Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.

Abstract: The present invention provides a method and structure for allowing more than 16 nodes to be configured in a single SONET BLSR network by utilizing unused portions of the transport overhead of an STS-N frame to expand the node identification field from 4 bits to 8 bits, thereby allowing up to 256 nodes to be present on a single ring.

Abstract: In accordance with the invention, a method and structure are provided for obtaining a ratio of M/(2.sup.N +K) by feeding various carry-out (and/or complemented carry-out) signals from full-adders back to various frequency control inputs of the full-adders to modify the denominator of the division ratio. By doing this, K additional or fewer counts are accumulated during each cycle. Thus, the denominator can be changed from 2.sup.N to 2.sup.N +K, where K can be either positive or negative to obtain the desired M/(2.sup.N +K) ratio.

Abstract: A distributed telecommunications switching system (100) is disclosed. The system includes a controller (140) that generates and transmits a cell stream with a plurality of reserved cells. A first switching subsystem (104) in communication with the controller (140) receives the cell stream and a first plurality of cells. The first switching subsystem (104) identifies the reserved cells in the cell stream and replaces selected ones of the reserved cells with selected ones of the first plurality of cells to produce a modified cell stream. The modified cell stream is transmitted to a second switching subsystem (102).

Abstract: A demultiplexer (10) includes an input stage (12) that receives a serial data stream having a plurality of m-bit sections at a first clock rate. The input stage converts successive n-bit portions of each m-bit section into a first n-bit parallel output at a second clock rate. An intermediary stage (14) receives the first n-bit parallel output and generates a second n-bit parallel output at the second clock rate. The first n-bit parallel output corresponds to a different portion of an m-bit section than the second n-bit parallel output. An output stage (16) receives the first n-bit parallel output from the input stage (12) and the second n-bit parallel output from the intermediary stage (14). The output stage (10) places the first n-bit parallel output onto an output bus (36) having a width of m-bitlines at an earlier instance in time than the placement of the second n-bit parallel output.

Abstract: A numerically controlled oscillator (10) includes a difference engine (12) that receives a numerator signal (14) and a numerator minus denominator signal (16). The numerator signal (14) and the numerator minus denominator signal (16) represent constant input values for a desired fractional relationship between a sine wave output signal (34) and a sample clock input signal (20) of numerically controlled oscillator (10). The difference engine (12) generates a difference output signal (18) that is received by a phase adder (22) for adding either a one or a zero to a combination of the delta phase input signal (24) and a phase accumulator output signal (26). The difference engine (12) optimally distributes ones and zeros so as to minimize phase jitter in the output signal (34).

Abstract: An open loop desynchronizer (10) includes a demapper (12) that reads asynchronous data from a synchronous channel (14) and writes this data to a first in first out buffer (18). The demapper (12) decodes deviations from a nominal stuff bit rate that indicates whether fewer or more stuff bits than data bits are needed on the synchronous channel (14) and generates a frequency deviation control signal (20) therefrom. The frequency deviation control signal (20) drives a digital filter (22) and a numerically controlled oscillator (24). The digital filter (22) and numerically controlled oscillator (24) generate a transmit clock (26) that tracks the asynchronous payload rate according to unit pulses on the frequency deviation control signal (20). The first in first out buffer (18) transmits the asynchronous data over a transmit data line (28) according to the asynchronous payload rate generated on the transmit clock (26).

Abstract: A finite impulse response filter (10) incorporates a two input data multiplexer (12) and a series of delay registers (18, 20, and 22) for processing input samples off an input data line (14). The data multiplexer (12) selects between a feedback sample generated at the last delay register (22) and an input sample received on the input data line (14). A multiplier (24) combines a coefficient as selected by a coefficient multiplexer (26) with the selected sample to drive an adder (28). The adder (28) sums sequential products from the multiplexer (24) to drive an accumulator register (30). The accumulator register (30) provides the adder (28) with the sum of products feedback in order that the adder (28) may sum successive products together. At the completion of a cycle, the data multiplexer (12) selects a new input sample off the input data line (14) and the adder (28) to accumulator register (30) combination is reset through a zero adjust generator (32).

Abstract: Apparatus and a method desynchronizes data by providing a high resolution FIFO depth measurement. A numerically controlled oscillator is combined with a FIFO memory to implement a variable frequency transmit clock signal having virtually unlimited frequency and phase resolution.