Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: The preferred embodiments described herein provide a method and system for automatically directing data in a computer network based on traffic demands. In one preferred embodiment, traffic demands of a computer network are determined, and data is automatically directed in the computer network based on the determined traffic demands. Other preferred embodiments are provided, and any or all of the preferred embodiments described herein can be used alone or in combination with one another.

Abstract: A cache subsystem for a computer system having a processor and a main memory is described. The cache subsystem includes a prefetch buffer coupled to the processor and the main memory. The prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor. The predicted address is based upon an address for a last memory fetch from the processor. A main cache is coupled to the processor and the main memory. The main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer. The main cache stores a second data fetched from the main memory in accordance with the address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address. The address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.

Abstract: A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.

Abstract: A method and apparatus for remapping of row addresses of memory requests to random access memory. A master device such as a central processing unit (CPU) issues a memory request comprising a memory address to the memory. The memory consists of multiple memory banks, each bank having a plurality of rows of memory elements. Associated with each memory bank is a sense amplifier latch which, in the present invention, functions as a row cache to the memory bank. The memory address issued as part of the memory request is composed of device identification bits to identify the memory bank to access, row bits which identify the row to access, and column address bits which identify the memory element within the row to access. When memory is to be accessed the row of data identified by the row bits is loaded into the sense amplifier latch and then is provided to the requesting master device.

Abstract: A slot determination mechanism wherein a number of bus units establish their positions along the bus and the total number of units on the bus. The units are connected in a bidirectional daisy chain. A one-cycle reset pulse is sent downstream to unit 1 (the upstream unit). Each unit on receiving one or more pulses from upstream sends that many plus one pulses downstream and then sends a one pulse upstream. Each unit then transmits upstream whatever it receives from downstream. The number of pulses received from upstream provide the slot number. The total number of pulses received from upstream and downstream provide the total number of units.

Abstract: Error reporting circuitry interrupts the CPU on the occurrence of a single bit memory error only when the chip member causing the error is different from the chip number that caused the previous error.

Abstract: Apparatus for decreasing the latency time associated with floating point addition and subtraction in a computer, using a novel bifurcated, pre-normalization/post-normalization approach that distinguishes between differences of floating point exponents.