Abstract: A high power Cobra interposer with an integrated guard plate, which is utilized for the testing of electrical products. The guard plate and the upper die of the interposer assembly are integrated into a single unit, thereby eliminating a portion of the structure. The Cobra structure utilizes a novel hole configuration in the upper die portion of the interposer structure, whereby only a small portion of the Cobra tip protrudes, rendering it less susceptible to being damaged in comparison with current designs.

Abstract: A method, system and apparatus for testing an integrated circuit chip. The system including: means for forming a liquid polyalphaolefine layer on a bottom surface of the integrated circuit chip, a top surface of the integrated circuit chip having and a bottom surface not having signal and power pads; means for placing a surface of a heat sink into physical contact with the bottom surface of the polyalphaolefine layer; means for electrically coupling the integrated circuit chip to a tester; means for electrically testing the integrated circuit chip; means for electrically de-coupling the integrated circuit chip from the tester; means for removing the heat sink from contact with the polyalphaolefine layer, all or a portion of the polyalphaolefine layer remaining on the bottom surface of the integrated circuit chip; and means for removing the polyalphaolefine layer from the bottom surface of the integrated circuit chip.

Abstract: A method, system and apparatus for testing an electronic device. The method including: (a) forming a temporary liquid heat transfer layer on a surface of the electronic device; after step (a), (b) placing a surface of a heat sink into physical contact with a surface of the heat transfer layer; after step (b), (c) electrically testing the electronic device; after step (c), (d) removing the heat sink from contact with the heat transfer layer; and after step (d), (e) removing any heat transfer layer remaining on the electronic device from the surface of the electronic device.

Abstract: A space transformer for use in an integrated circuit wafer test system, the space transformer including: a ground conductor; a power conductor; and one or more decoupling capacitors physically located between the ground conductor and the power conductor and electrically connected between a bottom surface of the ground conductor and a top surface of the power conductor.

Abstract: A space transformer for use in an integrated circuit wafer test system, the space transformer including: a ground conductor; a power conductor; and one or more decoupling capacitors physically located between the ground conductor and the power conductor and electrically connected between a bottom surface of the ground conductor and a top surface of the power conductor.

Abstract: A nonresilient rigid test probe arrangement which is designed for testing the integrity of silicon semiconductor device wafers or chips, and which eliminates pliant conditions encountered by current text fixtures, which are adverse to the attainment of satisfactory test results with rigid probes. The test system interface assembly includes a rigid ceramic substrate which forms a pedestal over which the rigid probe makes electrical contact. A PC board is located on the opposite side of the ceramic substrate. A clamp ring retains the PC board to a test head system with mating precision reference surfaces formed therebetween. Pogo pin connectors extend between the PC board and the test head system. A stiffening element having a control aperture is bolted through the PC board to the clamp ring, all of which form a rigid test probe arrangement.

Abstract: A probe system for electrical contact testing of a row of densely spaced wire bonding pads is provided comprising a plurality of probes, with each probe having a tip offset from the probe center axis. The probes may be mounted in a housing having an upper die and a lower die, and the lower die may be offset from the upper die. The probes are pivotally mounted in the holes of the upper die, and the probe bodies are convexly curved and extend down into the holes of the lower die. The bevel tipped probes may be arranged in two staggered and parallel rows of probes, with the tip of each probe oriented along the centerline formed between the two row of probes. The probes may be closely spaced in each row. The tips of the probes in one row are oriented 180 degrees with respect to the probes in the opposite row. The tips of each probe may also comprise a tip located along the center axis or a double bevel surface forming a tip at the apex of the two bevel surfaces.

Abstract: An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burn-in to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation.

Abstract: An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation.

Abstract: A vertical probe for use in testing multiple chips carried on a wafer comprises a body of dielectric material having a testing surface and an output surface spaced from the testing surface. The dielectric body includes at least one chamber defining an opening in the output surface, and the rim of the opening is formed by a lip of the dielectric material. The device also includes multiple contacts which pass through the testing surface and which are snap fit in holes in the rim. A unibody construction for the dielectric body is described.

Abstract: A cover assembly for a socket suitable to accommodate modules of varying thicknesses which can be advantageously used for final test and burn-in test is described. The assembly is characterized by having a low profile and includes a hinged lid; a floating shaft coupled to two cams pivoting on the floating shaft; a locking member positioned between the two cams for locking the hinged lid when in a closed position, the locking member pivoting about the floating shaft; a pressure plate for forcing the module into the socket; and stiffening members integral to the hinged lid located on opposing sides of the hinged lid and below the surface of the pressure plate for providing added strength to the assembly. The assembly also includes a heatsink inserted through an aperture located in the pressure plate, to directly contact the chip which is mounted on the module. The force applied to the chip is independent of the force applied to the module.

Abstract: A liquid interface cooling chuck assembly 10 includes a clamping section 12 having a top surface 16 with three separate cooling circuit grooves machined therein and a bottom surface 64 having a double spiral cooling circuit machined therein. The clamping section 12 is soldered to the flat top surface 18 of the support section 14 which as a bottom surface having structural ribs machined therein. Liquid is provided to the three cooling circuits of clamping section 12 to provide a liquid interface between a wafer and the top surface 16 of the clamping section 12. A cooling fluid is also circulated through the bottom surface cooling circuit.

Abstract: A semiconductor wafer, liquid interface clamping and cooling system 80 includes a chuck 10 having clamping section 12 with a top surface 16 with three clamping/cooling circuit grooves machined therein for providing a liquid interface between a wafer under test and the top surface 16. A bottom surface 64 of the clamping section has a double spiral cooling circuit machined therein for providing backside cooling. A source vessel 110 maintained at atmospheric pressure provides fluid to the top surface clamping/cooling circuits and a collection vessel 112 maintained at house vacuum pressure collects the fluid. A set of processor controlled valves 114, 118, 128, 130, 132, 141, 142 144, 158 and 164 control the fluid in a preprogrammed sequence. A chiller system 82 and pump 90 provide temperature regulated fluid flow to the clamping section 12 bottom surface 64.

Abstract: A wafer chuck temperature control system is disclosed for use in a semiconductor wafer testing apparatus. The wafer chuck is divided into a plurality of temperature sensor and cooling element domains corresponding to chip location regions of an overlying undiced wafer being tested. Computer scanning of the sensors determines which domain is the one harboring the heat source (chip under test) and selects the same for connection to a closed loop temperature control feedback servo. Provision also is made for introducing a helium gas interface between the wafer and the chuck by placing annular grooves in the face of the chuck through which the helium flows when the wafer is vacuum-seated against the chuck. A predetermined helium gas flow rate is maintained to preserve vacuum holddown and to optimize the thermal resistance of the wafer-chuck interface.