Abstract: Latch circuit and method which permit two-phase latches and flip-flops to be intermixed in a system having level sensitive scanning without critical clock requirements. The circuit includes a master latch having a normal data input and a scan data input, and a slave latch connected to the master latch. A differential pair of clock signals is applied to the latches in a complementary manner during a normal mode of operation to load data from the normal data input to the master latch and to transfer the normal data from the master latch to the slave latch, and two separate low frequency non-overlapping scan clock phases are applied to the latches during a level sensitive scanning mode to load data from the scan data input to the master latch and to transfer the scan data from the master latch to the slave latch.

Abstract: A self-timed random access memory circuit is designed on a single monolithic integrated circuit chip. The chip includes a random access memory including addressable storage locations, address decoding circuitry, data input and output circuitry and write enable circuitry. In addition, the chip includes input latches connected to chip input terminals which store data, address and operation control signals from off-chip circuitry in response to a timing signal, also from the off-chip circuitry. Also in response to the timing signal, an output latch on the chip stores data from the random access memory for transmission to output terminals, where the data is available to the off-chip circuitry. The input and output latches permit the self-timed random access memory circuit to perform in a pipelined manner.

Abstract: A memory control apparatus for use in a digital computer system. The computer system comprises a central processing unit and a main memory which has a plurality of memory units. The processor has control circuitry for simultaneously addressing a plurality of words stored in the memory locations in the memory units. The processor addresses the plurality of words by the combination of a memory address signal and word request control signal which are equal to the number of words to be transferred. While addressing of the memory units occurs in parallel, the transfer of words occurs serially. The initial word as defined by the memory address signal is transferred first with the remaining words transferred in ascending modulo four order. If one or more of the four words has not been requested, it is automatically skipped by the control apparatus with no loss in time or continuity.