Abstract: A timing circuit for a track following servo system wherein an odd servo track having a series of prerecorded odd dibits thereon and an adjacent even servo track having a series of even dibits prerecorded thereon are moved with respect to a servo head to induce in the servo head signals that vary with the occurrence of the dibits and have an amplitude representative of the lateral position of the servo head with respect to the servo tracks. The servo head and its associated preamplifier produce a first signal having portions from both odd and even servo tracks and a second signal that is the inverse of the first signal. The first and second signals are processed by parallel identical circuit paths to generate a clocking signal that times the remainder of the data storage system in synchronism with the spacing of dibits on the servo tracks.