Abstract: A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides.

Abstract: A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process.

Abstract: A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. An application program requiring graphics to be rendered is coded to bound a sequence of calls to basic rendering functions, defining a desired image to be rendered, between begin-program and end-program identifiers. When the application program is executed on a host operating system, a begin-program identifier invokes a function in a graphics device driver in the host system. The function captures the calls to the rendering functions within the application program in a memory as hardware instructions to the graphics subsystem. When the function encounters an end-program identifier, it registers the captured hardware instructions with the host system as an executable program.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Abstract: A system and method for decoupling graphics operations from a host processor to improve the efficiency of graphics rendering and free the host processor for other essential tasks. A processing system includes a host processor, a memory, a display list processor (DLP), graphics accelerators and display hardware. The host processor builds display lists generated by graphics applications and stores the display lists in the memory. The display lists include hardware function directives and control directives. The DLP accesses the memory to process the display lists, issuing the hardware function directives to the accelerators to generate display data.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Abstract: Hardware logic and processing methods for enhanced data manipulation within a graphics display system are described. The graphics display system includes a graphics processor sub-system and a rendering subsystem which are serially connected for pipeline processing of an interleaved stream of commands and data. One or more status bits or XBITs are defined within each rasterizer of a multi-rasterizer rendering sub-system. An XBIT, which may comprise a ZBIT, a UBIT, or an RBIT, etc., provides a mechanism for introducing execution of various logic functions within the rendering sub-system portion of the computer graphics adapter. Corresponding data processing methods are also described.

Abstract: A method and apparatus for the management of the data associated with multiple graphics contexts in a computer graphics rendering system. Graphics contexts are built by graphics engines and selectively saved into a context save RAM. Context switches are managed either by modifying a context base pointer to address a new section of the context save RAM, or by writing out a portion of the context save RAM to external storage and reading in a replacement context from external storage. The writing and reading process are managed by a control processor allowing the graphics engines to switch context at the same time. New contexts read from external storage automatically cause regeneration of downstream rasterization parameters.