Abstract: A field effect transistor having a highly doped gate wherein both the gate and the channel are different semiconductors with an energy band relationship that provides a barrier to both electrons and holes. The energy band relationship is staggered so that tunneling of electrons from the channel into the gate and holes from the gate into the channel is suppressed. An example structure is an InP light p conductivity type channel with a heavily doped AlInAs p.sup.++ conductivity type gate.

Abstract: A field induced base ballistic majority carrier transfer transistor is constructed of two regions of different bandgap semiconductors, each region having the same conductivity type but with the region with the smaller bandgap having a lower conductivity. An accumulation layer in the small bandgap semiconductor adjacent the larger bandgap semiconductor is produced by the bias voltage and serves as the base of the device. A source of emitted carriers is provided by a third region of higher conductivity on the external portion of the smaller bandgap region.

Abstract: A field effect transistor comprising a semiconductor channel region; an undoped semiconductor material region adjacent the channel region; a second semiconductor material region separated from the channel region; and a region of semiconductor material adjacent the second region and having a narrower band gap than the band gap of the region adjacent the channel region; and ohmic contact means to the region having the narrower band gap.

Abstract: A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate (14) is formed with a source terminal (22), a drain (24) terminal, and a gate terminal (26) upon an upper surface of a semiconductor chip. The chip includes a first layer (18) and a second layer (20), the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source region and the drain region. A pocket layer (16) is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement mode.

Abstract: A bipolar transistor device is disclosed having a structure wherein a layer of insulating material extends over and covers the structure substrate up to the region of the extrinsic base around the emitter. A very small area conductive base contact is provided to the extrinsic base, and a protective wall of insulating material is located on the sidewall of the base contact to isolate it from the emitter contact. This structure is made possible by a fabrication process incorporating a double-self-alignment technique wherein the base is self-aligned to a window in the insulating material and the emitter is self-aligned to the base.

Abstract: A Transistor-Transistor Logic (TTL) gate is disclosed wherein a different amount of base current is applied to the inverter transistor than is applied to the base of the output transistor. In one embodiment, a current mirror circuit controls the amount of base current flowing between the input transistor collector terminal and the base terminal of the inverter transistor to an amount less than that flowing between the input transistor collector terminal and the base terminal of the output transistor. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.