Patents by Inventor Paul Malachy Daly
Paul Malachy Daly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10580909Abstract: The present disclosure relates to a semiconductor photomultiplier comprising an array of interconnected microcells; wherein the array comprises at least a first type of microcell having a first junction region of a first geometric shape; and a second type of microcell having a second junction region of a second geometric shape.Type: GrantFiled: August 29, 2017Date of Patent: March 3, 2020Assignee: SENSL TECHNOLOGIES LTD.Inventors: Paul Malachy Daly, John Carlton Jackson
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Publication number: 20190067495Abstract: The present disclosure relates to a semiconductor photomultiplier comprising an array of interconnected microcells; wherein the array comprises at least a first type of microcell having a first junction region of a first geometric shape; and a second type of microcell having a second junction region of a second geometric shape.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: SensL Technologies Ltd.Inventors: Paul Malachy Daly, John Carlton Jackson
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Patent number: 10205033Abstract: The present disclosure relates to a semiconductor photomultiplier which comprises one or more microcells on a substrate having at least one terminal. At least one ESD protection element is operably coupled to the at least one terminal.Type: GrantFiled: December 14, 2017Date of Patent: February 12, 2019Assignee: SensL Technologies Ltd.Inventors: Paul Malachy Daly, John Carlton Jackson, Brian McGarvey, Stephen Bellis
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Patent number: 10043792Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.Type: GrantFiled: November 8, 2016Date of Patent: August 7, 2018Assignee: Analog Devices, Inc.Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
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Publication number: 20170117266Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.Type: ApplicationFiled: November 8, 2016Publication date: April 27, 2017Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
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Patent number: 9520486Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.Type: GrantFiled: November 4, 2009Date of Patent: December 13, 2016Assignee: Analog Devices, Inc.Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
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Patent number: 8513713Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.Type: GrantFiled: May 10, 2012Date of Patent: August 20, 2013Assignee: Analog Devices, Inc.Inventors: Paul Malachy Daly, Andrew David Bain, Derek Frederick Bowers, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson, William Allan Lane
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Patent number: 8476684Abstract: Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.Type: GrantFiled: September 29, 2010Date of Patent: July 2, 2013Assignee: Analog Devices, Inc.Inventors: Edward John Coyne, Paul Malachy Daly, Jagar Singh, Seamus Whiston, Patrick Martin McGuinness, William Allan Lane
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Patent number: 8390039Abstract: A field effect transistor having a drain, a gate and a source, where the drain and source are formed by semiconductor regions of a first type, and in which a further doped region is provided intermediate the gate and the drain. Field gradients around the drain are thereby reduced.Type: GrantFiled: November 2, 2009Date of Patent: March 5, 2013Assignee: Analog Devices, Inc.Inventors: Derek Frederick Bowers, Andrew David Bain, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson, William Allan Lane
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Patent number: 8357985Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.Type: GrantFiled: January 13, 2012Date of Patent: January 22, 2013Assignee: Analog Devices, Inc.Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson
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Patent number: 8350352Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.Type: GrantFiled: November 2, 2009Date of Patent: January 8, 2013Assignee: Analog Devices, Inc.Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson
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Patent number: 8263469Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.Type: GrantFiled: October 6, 2011Date of Patent: September 11, 2012Assignee: Analog Devices, Inc.Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
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Publication number: 20120217551Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.Type: ApplicationFiled: May 10, 2012Publication date: August 30, 2012Applicant: Analog Devices, Inc.Inventors: Paul Malachy Daly, Andrew David Bain, Derek Frederick Bowers, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, Bernard Patrick Stenson, William Allan Lane
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Patent number: 8193046Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.Type: GrantFiled: November 2, 2009Date of Patent: June 5, 2012Assignee: Analog Devices, Inc.Inventors: Paul Malachy Daly, Andrew David Bain, Derek Frederick Bowers, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson, William Allan Lane
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Publication number: 20120112307Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.Type: ApplicationFiled: January 13, 2012Publication date: May 10, 2012Applicant: ANALOG DEVICES, INC.Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson
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Publication number: 20120074493Abstract: Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.Type: ApplicationFiled: September 29, 2010Publication date: March 29, 2012Applicant: ANALOG DEVICES, INC.Inventors: Edward John Coyne, Paul Malachy Daly, Jagar Singh, Seamus Whiston, Patrick Martin McGuinness, William Allan Lane
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Patent number: 8120136Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.Type: GrantFiled: November 2, 2009Date of Patent: February 21, 2012Assignee: Analog Devices, Inc.Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, Bernard Patrick Stenson
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Publication number: 20120028432Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.Type: ApplicationFiled: October 6, 2011Publication date: February 2, 2012Applicant: Analog Devices, Inc.Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
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Patent number: 8058704Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.Type: GrantFiled: November 2, 2009Date of Patent: November 15, 2011Assignee: Analog Devices, Inc.Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
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Publication number: 20110101486Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.Type: ApplicationFiled: November 2, 2009Publication date: May 5, 2011Applicant: Analog Devices, Inc.Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, Bernard Patrick Stenson