Abstract: A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.

Abstract: A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

Abstract: A computer system is disclosed that includes: a communications bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the communications bus; a send machine coupled between a host processor and the bus controller; and a first-in first-out (FIFO) buffer coupled to the send machine and coupled between the host processor and the bus controller.

Abstract: A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.

Abstract: A method for writing a servo pattern onto a length of magnetic tape includes writing a first frequency signal onto a first portion along the length of the tape, and writing a second frequency signal by simultaneously writing a plurality of spaced apart predetermined shapes. The predetermined spaced apart shapes are achieved by writing the second frequency using a writer having a split top pole. Passing the tape over the spaced apart top pole elements allows the writer to simultaneously write the plurality of spaced apart shapes. The tape can then be passed over a read module.

Abstract: A servo stripe pattern for determining the longitudinal position of the tape with respect to the tape head. A data field on each frame of the servo pattern includes a digital one or a zero. An adjacent series of data fields are arranged in a predetermined sequence defining synchronization and position count fields. The position count field allows the tape controller to accurately determine where, along the length of the tape, the tape head is currently positioned.

Abstract: A magnetic tape servo pattern with different frequency signals to define the frame boundary. A significantly different frequency field is used to signal the transition from one frame to the next.

Abstract: A magnetic tape servo pattern including track identification. Information from a track identification area intersecting one or more tracks on each frame in combination with information identifying the track as odd or even, is used to uniquely identify the track.

Abstract: A method for detecting a frame edge in a servo stripe on a length of magnetic tape. The method includes converting an analog signal to a digital signal and detecting a change in digital signal frequency at a frame edge. A detection signal is generated in response to the detected frequency change.

Abstract: A thin film magnetic tape head including a split top pole. The split top pole configuration allows multiple patterns to be written simultaneously onto a servo band.

Abstract: A method for identifyng a servo track. Information from the servo track about the odd or even number of the track is combined with information about the presence or absence of a track identification area to identify the track number.

Abstract: A method for determining the longitudinal position of a length of magnetic tape with respect to the tape head. A data field on each frame of the servo stripe includes a digital one or a zero. An adjacent series of data fields are arranged in a predetermined sequence defining synchronization and position count fields. Identifying the position count field allows the tape controller to accurately determine where, along the length of the tape, the tape head is currently positioned.

Abstract: A magnetic tape servo pattern including track identification. Information from a track identification area intersecting one or more tracks on each frame in combination with information identifying the track as odd or even, is used to uniquely identify the track.

Abstract: Oxygen is introduced onto the surface of a molten ferrous metal through at least one water-cooled lance disposed above the melt surface while an oxygen free gas in which is entrained ground solids is intermittently introduced into the molten ferrous metal through tuyeres disposed below the melt surface.