Patents by Inventor Paul Marella

Paul Marella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080081385
    Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
    Type: Application
    Filed: November 14, 2007
    Publication date: April 3, 2008
    Inventors: Paul Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar Kekare, Carl Hess
  • Publication number: 20050052643
    Abstract: Methods and systems for inspection of a specimen using different parameters are provided. One computer-implemented method includes determining optimal parameters for inspection based on selected defects. This method also includes setting parameters of an inspection system at the optimal parameters prior to inspection. Another method for inspecting a specimen includes illuminating the specimen with light having a wavelength below about 350 nm and with light having a wavelength above about 350 nm. The method also includes processing signals representative of light collected from the specimen to detect defects or process variations on the specimen. One system configured to inspect a specimen includes a first optical subsystem coupled to a broadband light source and a second optical subsystem coupled to a laser. The system also includes a third optical subsystem configured to couple light from the first and second optical subsystems to an objective, which focuses the light onto the specimen.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 10, 2005
    Inventors: Steve Lange, Paul Marella, Nat Ceglio, Shiow-Hwei Hwang, Tao-Yi Fu
  • Publication number: 20050004774
    Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
    Type: Application
    Filed: July 1, 2004
    Publication date: January 6, 2005
    Inventors: William Volk, James Wiley, Sterling Watson, Sagar Kekare, Carl Hess, Paul Marella, Sharon McCauley, Ellis Chang
  • Patent number: 5804004
    Abstract: A method for fabricating a multichip module includes attaching a first integrated circuit to a silicon circuit board. Bonding pads on the first integrated circuit are wire-bonded to a first set of contacts on the circuit board. A second integrated circuit is adhesively attached onto the top of the first integrated circuit. The second integrated circuit includes a recessed bottom surface to provide an overhang over the first integrated circuit which exposes the bonding pads on the top surface of the first integrated circuit. Then bonding pads on the second integrated circuit are wire-bonded to a second set of contacts on the circuit board.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: September 8, 1998
    Assignee: nChip, Inc.
    Inventors: David B. Tuckerman, Nicholas E. Brathwaite, Paul Marella, Kirk Flatow