Abstract: A multi-chip module (MCM) includes chip sub-modules that are fabricated as self-contained testable entities. The chip sub-modules plug into respective sockets in a frame of the MCM. Each chip sub-module may be tested before being plugged into the MCM. A chip sub-module may include an IC chip, such as a processor, mounted to an sub-module organic substrate that provides interconnects to the chip. The frame into which each chip sub-module plugs sits on a mini-card organic substrate that interconnects the chip sub-modules together. The MCM may include a downstop between the mini-card organic substrate and a system board to limit or prevent solder creep of solder connections between the mini-card organic substrate and the system board.

Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.

Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.

Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.

Abstract: A methodology to determine a bit pattern that may excite a worse case or near worse case simultaneous switching noise on a memory or input/output (IO) interface of a digital system is provided. This methodology involves determining an impedance profile of the IO interface of the digital system. The amplitude response of signal X(f) may be matched in the impedance profile of the IO interface. The phase response of the signal X(f) is also set. The signal X(f) having a matched amplitude response may be converted from a frequency domain signal to a time domain signal to produce a signal X(t). Signal X(t) the time domain signal X(t) may be digitized to represent a bit stream B(t).

Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.

Abstract: A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement.

Abstract: The present invention provides for a balanced laminated integrated circuit package. The package includes a two metal layer bumped circuit, a first adhesive layer having a thickness on a first side of the bumped circuit, a first outer conductive layer having a thickness bonded to the first adhesive layer and a second adhesive layer having a thickness substantially equal to the thickness of the first adhesive layer on a second side of the bumped circuit. The invention also includes a second outer conductive layer bonded to the second adhesive layer, the second outer conductive layer having a thickness substantially equal to the thickness of the first outer conductive layer.

Abstract: The present invention provides for a method of interconnecting a bumped circuit having relatively fine traces to an overlying conductive layer of a laminated circuit assembly. The overlying conductive layer is laminated with a suitable insulating adhesive over a bumped relatively fine pitch circuit layer. In the general vicinity of the desired power connection, a window substantially larger than the width of the bump is etched away from the conductive material of the trace of the outer conductive layer and the adhesive is plasma etched to expose the elevated portion of the desired bump of the bumped circuit. A conductive media such as conductive polymer or solder is then applied at the etched window of the overlying relatively coarse trace, which ensures an electrical connection between the exposed portion of the bump and the overlying trace.

Abstract: Disclosed is an apparatus which shows the use of an inwardly disposed set of C4 type I/O connections to an integrated circuit chip over and above the typical peripherally disposed set of I/O connections which use wire type connections between the chip and other circuitry of a substrate upon which the chip is mounted. The inwardly disposed set of connections may be used to provide a direct connection to an optional ancillary chip having a corresponding set of I/O connection points. Such a construction not only increases the number of possible I/O connections, but additionally increases the bandwidth of communications between the directly connected chips.

Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.

Abstract: The present invention provides for a balanced laminated integrated circuit package. The package includes a two metal layer bumped circuit, a first adhesive layer having a thickness on a first side of the bumped circuit, a first outer conductive layer having a thickness bonded to the first adhesive layer and a second adhesive layer having a thickness substantially equal to the thickness of the first adhesive layer on a second side of the bumped circuit. The invention also includes a second outer conductive layer bonded to the second adhesive layer, the second outer conductive layer having a thickness substantially equal to the thickness of the first outer conductive layer.

Abstract: The present invention provides for a method of interconnecting a bumped circuit having relatively fine traces to an overlying conductive layer of a laminated circuit assembly. The overlying conductive layer is laminated with a suitable insulating adhesive over a bumped relatively fine pitch circuit layer. In the general vicinity of the desired power connection, a window substantially larger than the width of the bump is etched away from the conductive material of the trace of the outer conductive layer and the adhesive is plasma etched to expose the elevated portion of the desired bump of the bumped circuit. A conductive media such as conductive polymer or solder is then applied at the etched window of the overlying relatively coarse trace, which ensures an electrical connection between the exposed portion of the bump and the overlying trace.

Abstract: An interlayer connection for electrically connecting first and second conductive elements and reducing interlayer registration requirements is disclosed. The interlayer connection includes a first layer including a first electrically conductive element, a second layer including a second electrically conductive element, and a third layer disposed between the first layer and the second layer. The third layer includes an electrically insulative portion having a matrix of immediately adjacent vias therethrough. A selected plurality of immediately adjacent vias within the matrix are disposed between the first and the second electrically conductive elements and contain electrically conductive material forming a conductive path between the first and the second electrically conductive elements.

Abstract: An interlayer connection for electrically connecting first and second conductive elements and reducing interlayer registration requirements is disclosed. The interlayer connection includes a first layer including a first electrically conductive element, a second layer including a second electrically conductive element, and a third layer disposed between the first layer and the second layer. The third layer includes an electrically insulative portion having a matrix of immediately adjacent vias therethrough. A selected plurality of immediately adjacent vias within the matrix are disposed between the first and the second electrically conductive elements and contain electrically conductive material forming a conductive path between the first and the second electrically conductive elements.