Abstract: A technique self tests a memory system having memory modules that operate at a normal operating clock rate during a normal operating mode. Each memory module has multiple arrays of synchronous dynamic random access memory devices. The technique involves obtaining, independently of a central controller, time phase identifiers that respectively correspond to the memory modules, and reducing the normal operating clock rate to a reduced clock rate. The technique further involves executing, in the memory modules, self test transactions in different time phases depending on the obtained time phase identifiers. The memory modules initiate execution of self test transactions at the reduced clock rate. Multiple memory modules execute self test transactions in each of the different time phases. Each memory module executes self test transactions that alternately access the multiple arrays of that memory module.

Abstract: An adjustable filter for a computing system having memory error detecting and correcting features selectively masks user-specified errors, thereby preventing storage of such errors in a control and status register (CSR). The invention includes a command and data register 102; a CSR 103; an error detecting and correcting circuit 108, including a check bit generator 108a, an error detecting circuit 108b, and an error correcting circuit 108c; a memory module 114; and filter logic 300. The contents of a filter control register 220 of the CSR 103 operate to specify a particular error which is to be "filtered". The filter logic 300 includes a plurality of logic gates that compare the user-specified signals stored in the register 220 with error-related signals reported by the error detecting circuit 108b. If the signals match, information associated with the detected error is prevented from being stored in the CSR 103.