Patents by Inventor Paul Martinez
Paul Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250066377Abstract: The present invention provides novel amino chromen-2-one compounds that are inhibitors of mitochondrial RNA polymerase for treating various diseases such as cancer and others associated with metabolic disorders and mitochondrial dysfunction.Type: ApplicationFiled: December 19, 2022Publication date: February 27, 2025Applicant: Pretzel Therapeutics, Inc.Inventors: Andrew Griffin, Paul S. Charifson, Jeremy Green, Gabriel Martinez Botella
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Publication number: 20250059214Abstract: Disclosed are compounds according to Formula (1) which inhibit LONP1, and pharmaceutical compositions comprising compounds of the disclosure. Compounds and pharmaceutical compositions of the disclosure may be useful for the treatment of diseases and disorders associated with LONP1, including oncologic diseases and disorders, such as cancer, and diseases and disorders related to mitochondrial dysfunction, such as neurodegenerative disorders, metabolic disorders, and diseases associated with the aging process. The disclosure also relates to methods of using such compounds and compositions for the treatment of such diseases and disorders.Type: ApplicationFiled: December 6, 2022Publication date: February 20, 2025Applicant: Pretzel Therapeutics, Inc.Inventors: Jeremy Green, Paul Charifson, Gabriel Martinez Botella, Andrew Griffin
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Publication number: 20250059213Abstract: Disclosed are compounds according to Formula (1) and Formula (2) which inhibit LONP1, and pharmaceutical compositions comprising compounds of the disclosure. Compounds and pharmaceutical compositions of the disclosure may be useful for the treatment of diseases and disorders associated with LONP1, including oncologic diseases and disorders, such as cancer, and diseases and disorders related to mitochondrial dysfunction, such as neurodegenerative disorders, metabolic disorders, and diseases associated with the aging process. The disclosure also relates to methods of using such compounds and compositions for the treatment of such diseases and disorders.Type: ApplicationFiled: December 6, 2022Publication date: February 20, 2025Applicant: Pretzel Therapeutics, Inc.Inventors: Jeremy Green, Paul Charifson, Gabriel Martinez Botella, Andrew Griffin
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Patent number: 10925164Abstract: Methods and systems for producing circuitry using stackable passive components are discussed. More specifically, the present disclosure provides designs and fabrication methods for production of stackable devices that may be used as components in circuitry such as filters and impedance matching adaptors. Such components may be used to save space in printed circuit boards. Moreover, stackable passive components may be dual components, which may be improve the electrical performance in certain types of circuits such as matched component filters.Type: GrantFiled: September 12, 2017Date of Patent: February 16, 2021Assignee: Apple Inc.Inventors: Paul A. Martinez, Curtis C. Mead, Scott D. Morrison, Giancarlo F. De La Cruz, Lin Chen, Albert Wang, Brad W. Simeral
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Publication number: 20200390285Abstract: An improved herb grinder system is described. Some implementations can include an herb grinder designed to keep ground material from drying out by providing moisture to an interior area of the grinder, where the moisture is delivered via packets or other suitable devices to keep the ground material in a moist environment. In some implementations, the grinder is modular to permit various aspects or configurations to be modified and adjusted for optimal performance of ground material storage. The herb grinder system can provide storage times that can vary from a few hours to days or longer by maintaining or increasing moisture levels to help preserve the quality of ground material.Type: ApplicationFiled: June 11, 2019Publication date: December 17, 2020Inventor: Paul Martinez Galaviz
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Patent number: 10811192Abstract: Multilayer ceramic capacitor structures may include structural arrangements, materials, and/or substrate modifications that can improve the reliability of the capacitor for long-term usage when faced with environmental stress. Embodiments may implement reduced entryways in the termination patterns of the capacitor to decrease damage potential due to exposure of moisture. Embodiments may implement structures that decrease interfaces with different physical characteristics, which may lead to a reduction in the formation of micro-fractures during regular usage. Methods of manufacture for the features that improve reliability are also detailed.Type: GrantFiled: September 28, 2018Date of Patent: October 20, 2020Assignee: Apple Inc.Inventors: Paul A. Martinez, Won Seop Choi, Gang Ning, Chirag V. Shah, Martin Schauer, Curtis C. Mead, Ming Yuan Tsai, Albert Wang
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Publication number: 20200105473Abstract: Multilayer ceramic capacitor structures may include structural arrangements, materials, and/or substrate modifications that can improve the reliability of the capacitor for long-term usage when faced with environmental stress. Embodiments may implement reduced entryways in the termination patterns of the capacitor to decrease damage potential due to exposure of moisture. Embodiments may implement structures that decrease interfaces with different physical characteristics, which may lead to a reduction in the formation of micro-fractures during regular usage. Methods of manufacture for the features that improve reliability are also detailed.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Paul A. Martinez, Won Seop Choi, Gang Ning, Chirag V. Shah, Martin Schauer, Curtis C. Mead, Ming Yuan Tsai, Albert Wang
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Systems and methods for determining an intensity level of an exercise using photoplethysmogram (PPG)
Patent number: 10512406Abstract: Disclosed systems and methods relate to determining an intensity level of an exercise using a photoplethysmogram (PPG) sensor. A method of determining an intensity level of an exercise for a user according to one embodiment of the present disclosure includes detecting, by a device, body signals from the user using a PPG sensor. The method includes determining, by the device, a heart rate of the user based on the body signals. The method includes determining, by the device, an error in the heart rate. The method also includes determining, by the device, the intensity level of the exercise for the user based at least on the error.Type: GrantFiled: August 31, 2017Date of Patent: December 24, 2019Assignee: Apple Inc.Inventors: Paul A. Martinez, Tim P. D'Angelo, Justin P. Dobson, Kevin B. Jessop, Jose A. Castillo -
Patent number: 10510492Abstract: Monolithic capacitor structures having a main capacitor and a vise capacitor are discussed. The vise capacitor provides to the monolithic capacitor structure reduced vibrations and/or acoustic noise due to piezoelectric effects. To that end, vise capacitor may cause piezoelectric deformations that compensate the deformations that are caused by the electrical signals in the main capacitor. Embodiments of these capacitor structures may have the main capacitor and the vise capacitor sharing portions of a rigid dielectric. Electrical circuitry that employs the vise capacitor to reduce noise and/or vibration in the monolithic capacitor structures is also described. Methods for fabrication of these capacitors are discussed as well.Type: GrantFiled: May 19, 2017Date of Patent: December 17, 2019Assignee: APPLE INC.Inventors: Ming Y. Tsai, Albert Wang, Curtis C. Mead, Tyler S. Bushnell, Paul A. Martinez
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Patent number: 10461040Abstract: Capacitor devices having multiple capacitors with similar nominal capacitances are described. The capacitors may be multilayer ceramic capacitors (MLCCs) and may be fabricated employing class 2 materials. The arrangement of the electrodes in the device may reduce relative variations between the capacitors of the device. The capacitor devices may be allow high performance and compact electrical circuits that may employ matched capacitors.Type: GrantFiled: June 28, 2017Date of Patent: October 29, 2019Assignee: APPLE INC.Inventors: Paul A. Martinez, Ming Y. Tsai, Won Seop Choi
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Patent number: 10431382Abstract: A printed circuit board (PCB) assembly having several electronic components mounted on a PCB and a damping layer covering the electronic components, is disclosed. Embodiments of the PCB assembly include an overmold layer constraining the damping layer against the PCB. Embodiments of the PCB assembly include an interposer between a capacitor of the electronic components and the PCB. Other embodiments are also described and claimed.Type: GrantFiled: August 31, 2015Date of Patent: October 1, 2019Assignee: Apple Inc.Inventors: Gemin Li, Paul Martinez, Benjamin A. Bard, Connor R. Duke, Zhong-Qing Gong, Kevin R. Richardson, Curtis C. Mead, Kieran Poulain, Sung Woo Yoo, Nelson J. Kottke
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Patent number: 10424438Abstract: Systems and methods described in this disclosure are related to fabrication and utilization of two-terminal electrical components that may have terminations with reduced width. Components, such as the ones described herein may be used to increase the density of components in electrical devices, as they may reduce a separation distance between devices that lead to solder bridging. Methods for fabrication are also described, including the use of ceramic layers that may provide reduction in parasitic capacitance and/or inductances.Type: GrantFiled: September 24, 2016Date of Patent: September 24, 2019Assignee: APPLE INC.Inventors: Paul A. Martinez, Curtis C. Mead, Scott D. Morrison, Giancarlo F. De La Cruz, Lin Chen, Albert Wang, Brad W Simeral, Vu Vo, Wyeman Chen
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Patent number: 10332683Abstract: Capacitor devices with electrodes that are geometrically arranged to reduce parasitic capacitances are described. The capacitors may be multilayer ceramic capacitor (MLCC) structures in which certain electrodes may have a clearance from a capacitor structure wall, such as top wall. In circuits and devices where that particular capacitor wall may be placed near a shielding structure, the clearance may reduce unintended parasitic capacitances between the shield structure and the electrodes. As a result, the shield structures may be placed closer to the electronic components, which may allow circuit boards and electronic devices with a lower profile.Type: GrantFiled: September 27, 2017Date of Patent: June 25, 2019Assignee: Apple Inc.Inventors: Behzad Reyhani Masoleh, Ming Y. Tsai, Paul A. Martinez, Scott D. Morrison, Tracey L. Chavers
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Patent number: 10256036Abstract: A system includes a circuit board, an inductor including windings mounted on the circuit board, and a plurality of magnetic field containment devices. Each magnetic field containment device includes an independent electrical circuit that is not directly electrically connected via a conductor to any other magnetic field containment device. Each magnetic field containment device also includes a material of a certain relative permeability. Each magnetic field containment device at least partially surrounds the inductor and, in operation, at least partially contains a magnetic B-Field generated by electrical current in the windings of the inductor. The plurality of magnetic field containment devices, in operation, enables a certain saturation current in the inductor.Type: GrantFiled: January 12, 2017Date of Patent: April 9, 2019Assignee: APPLE INC.Inventors: Paul A. Martinez, Ming Y. Tsai, Federico P. Centola, Martin Schauer, Cheung-Wei Lam, Jason C. Sauers
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Publication number: 20190096581Abstract: Capacitor devices with electrodes that are geometrically arranged to reduce parasitic capacitances are described. The capacitors may be multilayer ceramic capacitor (MLCC) structures in which certain electrodes may have a clearance from a capacitor structure wall, such as top wall. In circuits and devices where that particular capacitor wall may be placed near a shielding structure, the clearance may reduce unintended parasitic capacitances between the shield structure and the electrodes. As a result, the shield structures may be placed closer to the electronic components, which may allow circuit boards and electronic devices with a lower profile.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventors: Behzad Reyhani Masoleh, Ming Y. Tsai, Paul A. Martinez, Scott D. Morrison, Tracey L. Chavers
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Publication number: 20190075655Abstract: Methods and devices related to the design and fabrication of molded cores for printed circuit board assemblies and system-on-package (SIP) devices are discussed. The discussed printed circuit board assemblies may have multiple electrical components embedded in a molded core matrix and forming electrical connections with one or more printed circuit boards attached to the molded core matrix. Methods for sourcing of electrical components and production of the molded cores and printed circuit board assemblies are also discussed. The methods and devices may increase a volumetric density of electrical components in printed circuit board assemblies and provide improved mechanical properties to the electrical circuit device.Type: ApplicationFiled: November 8, 2018Publication date: March 7, 2019Inventors: Albert Wang, Paul A. Martinez
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Patent number: 10199172Abstract: Methods and devices related to fabrication and utilization of multilayer capacitors presenting coaxially arranged electrode layers. The capacitors may be self-shielded against electromagnetic interference with neighboring components. The capacitors may have reduced losses from fringing effects when compared to conventional capacitors. The coaxial capacitors may be two-terminal multilayer ceramic capacitors (MLCC). The design of the capacitors may facilitate an improved relationship between the electric and magnetic fields generated by the capacitor within the dielectric in some embodiments. In some embodiments, the placement of the terminals may lead to a cancelation of mutual inductances between the electrodes. Terminations that facilitate the coupling of the capacitor to a circuit board, as well as methods for fabrication of the capacitors are also discussed.Type: GrantFiled: September 24, 2016Date of Patent: February 5, 2019Assignee: Apple Inc.Inventors: Paul A. Martinez, Jason C. Sauers, Cheung-Wei Lam, Federico P. Centola, Andro Radchenko, Martin Schauer
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Patent number: 10179254Abstract: This application relates to capacitors that resist deformation because of the configuration of their conductive and dielectric layers. The capacitors are multilayer capacitors that include multiple dielectric and conductive layers. The dielectric layers can be arranged in a way that creates a rigid barrier or dead zone, which can resist mechanical deformation when the multilayer capacitor is charged. In some embodiments, two or more multilayer capacitors are stacked together in an arrangement that causes each of the multilayer capacitors to cancel any deformations of the other when the multilayer capacitors are charged. In this way, noise exhibited by the multilayer capacitors can be reduced.Type: GrantFiled: March 31, 2016Date of Patent: January 15, 2019Assignee: aPPLE INC.Inventors: Paul A. Martinez, Jason C. Sauers, Shawn X. Arnold
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Publication number: 20190006287Abstract: Capacitor devices having multiple capacitors with similar nominal capacitances are described. The capacitors may be multilayer ceramic capacitors (MLCCs) and may be fabricated employing class 2 materials. The arrangement of the electrodes in the device may reduce relative variations between the capacitors of the device. The capacitor devices may be allow high performance and compact electrical circuits that may employ matched capacitors.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Paul A. Martinez, Ming Y. Tsai, Won Seop Choi
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Publication number: 20180337003Abstract: Monolithic capacitor structures having a main capacitor and a vise capacitor are discussed. The vise capacitor provides to the monolithic capacitor structure reduced vibrations and/or acoustic noise due to piezoelectric effects. To that end, vise capacitor may cause piezoelectric deformations that compensate the deformations that are caused by the electrical signals in the main capacitor. Embodiments of these capacitor structures may have the main capacitor and the vise capacitor sharing portions of a rigid dielectric. Electrical circuitry that employs the vise capacitor to reduce noise and/or vibration in the monolithic capacitor structures is also described. Methods for fabrication of these capacitors are discussed as well.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Inventors: Ming Y. Tsai, Albert Wang, Curtis C. Mead, Tyler S. Bushnell, Paul A. Martinez