Patents by Inventor Paul Master

Paul Master has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250192982
    Abstract: A system and method to reduce fast Fourier transforms (FFT) required for bootstrapping in a Fully Homomorphic Encryption process. Ciphertext is separated into a vector of n samples. A fast Fourier transfer (FFT) is performed over a first vector of the samples. An FFT is performed for each of n polynomial terms multiplied by a bootstrap key. A point wise multiplication of each of the FFT outputs of the FFTs of the polynomial terms and the output of the FFT over the vector of the n samples is performed. The result of the FFT over the vector of the n samples is added to the results of the set of pointwise multiplications. An inverse FFT (IFFT) is performed on the FFT over the vector of n samples and the accumulated results of the point-wise multiplications to obtain a bootstrapping result of the ciphertext.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Fa-Long Luo, Paul Master
  • Publication number: 20250190570
    Abstract: A system and method to reduce fast Fourier transforms (FFT) required for bootstrapping in a Fully Homomorphic Encryption process. Ciphertext is separated into a vector of n samples. A fast Fourier transfer (FFT) is performed over a first vector of the samples and a FFT over a bootstrap key. A phase vector of n W(a) terms that are equivalents to the output of a FFT is calculated. A first set of pointwise multiplications of the FFT of the first vector of samples with each of the n W(a) terms in the phase vector is performed. A second set of pointwise multiplications of the results of the first set of pointwise multiplications with the FFT of the bootstrap key is performed. An inverse FFT(IFFT) on the accumulated result of the second set of point-wise multiplications is performed to obtain a bootstrapping result of the ciphertext.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Fa-Long Luo, Paul Master
  • Publication number: 20250147921
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Application
    Filed: December 12, 2024
    Publication date: May 8, 2025
    Inventors: Solomon Harsha, Paul Master
  • Patent number: 12174784
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: December 24, 2024
    Assignee: CORNAMI, INC.
    Inventors: Solomon Harsha, Paul Master
  • Publication number: 20240070114
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Inventors: Solomon Harsha, Paul Master
  • Patent number: 11853256
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 26, 2023
    Assignee: CORNAMI, INC.
    Inventors: Solomon Harsha, Paul Master
  • Patent number: 11055103
    Abstract: A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 6, 2021
    Assignee: Cornami, Inc.
    Inventors: Frederick Furtek, Paul Master
  • Patent number: 10333860
    Abstract: In accordance with a method a plurality of subscriber systems are provided, the systems being coupled via a Wide Area Network (WAN) and comprising a first subscriber system. The first subscriber system has processing and non-volatile storage and is suitably programmed for providing a subscriber service to a first subscriber. The first system is disposed in an unsecured location, which is associated with the first subscriber. Subsequently, the subscriber service is provided to the first subscriber. Separately, a task is provided to the first subscriber system via the WAN and is executed on the first subscriber system. An activity record for the execution of the task is logged, based on an amount of at least one of the processing and the non-volatile storage consumed on the first subscriber system during execution of the task.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: June 25, 2019
    Assignee: LEONOVUS USA
    Inventors: Daniel Willis, Paul Master, Gordon Campbell, Sean O'Hagan, Derek Noble
  • Patent number: 10318260
    Abstract: A method and system of compiling and linking source stream programs for efficient use of multi-node devices. The system includes a compiler, a linker, a loader and a runtime component. The process converts a source code stream program to a compiled object code that is used with a programmable node based computing device having a plurality of processing nodes coupled to each other. The programming modules include stream statements for input values and output values in the form of sources and destinations for at least one of the plurality of processing nodes and stream statements that determine the streaming flow of values for the at least one of the plurality of processing nodes. The compiler converts the source code stream based program to object modules, object module instances and executables. The linker matches the object module instances to at least one of the multiple cores.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 11, 2019
    Assignee: Cornami, Inc.
    Inventors: Frederick Furtek, Paul Master
  • Patent number: 10212483
    Abstract: In accordance with a method a plurality of subscriber systems are provided, the systems being coupled via a Wide Area Network (WAN) and comprising a first subscriber system. The first subscriber system has processing and non-volatile storage and is suitably programmed for providing a subscriber service to a first subscriber. The first system is disposed in an unsecured location, which is associated with the first subscriber. Subsequently, the subscriber service is provided to the first subscriber. Separately, a task is provided to the first subscriber system via the WAN and is executed on the first subscriber system. An activity record for the execution of the task is logged, based on an amount of at least one of the processing and the non-volatile storage consumed on the first subscriber system during execution of the task.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 19, 2019
    Assignee: LeoNovus Inc.
    Inventors: Daniel Willis, Paul Master, Gordon Campbell, Sean O'Hagan, Derek Noble
  • Publication number: 20190004813
    Abstract: A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 3, 2019
    Inventors: Frederick Furtek, Paul Master
  • Publication number: 20180293206
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Applicant: CORNAMI, INC.
    Inventors: Solomon Harsha, Paul Master
  • Patent number: 10073700
    Abstract: A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: September 11, 2018
    Assignee: Cornami, Inc.
    Inventors: Frederick Furtek, Paul Master
  • Publication number: 20180225102
    Abstract: A method and system of compiling and linking source stream programs for efficient use of multi-node devices. The system includes a compiler, a linker, a loader and a runtime component. The process converts a source code stream program to a compiled object code that is used with a programmable node based computing device having a plurality of processing nodes coupled to each other. The programming modules include stream statements for input values and output values in the form of sources and destinations for at least one of the plurality of processing nodes and stream statements that determine the streaming flow of values for the at least one of the plurality of processing nodes. The compiler converts the source code stream based program to object modules, object module instances and executables. The linker matches the object module instances to at least one of the multiple cores.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Frederick Furtek, Paul Master
  • Patent number: 10019410
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 10, 2018
    Assignee: CORNAMI, INC.
    Inventors: Solomon Harsha, Paul Master
  • Publication number: 20180095931
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Application
    Filed: April 6, 2017
    Publication date: April 5, 2018
    Inventors: Solomon Harsha, Paul Master
  • Patent number: 9934011
    Abstract: A method and system of compiling and linking source stream programs for efficient use of multi-node devices. The system includes a compiler, a linker, a loader and a runtime component. The process converts a source code stream program to a compiled object code that is used with a programmable node based computing device having a plurality of processing nodes coupled to each other. The programming modules include stream statements for input values and output values in the form of sources and destinations for at least one of the plurality of processing nodes and stream statements that determine the streaming flow of values for the at least one of the plurality of processing nodes. The compiler converts the source code stream based program to object modules, object module instances and executables. The linker matches the object module instances to at least one of the multiple cores.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: April 3, 2018
    Assignee: Cornami, Inc.
    Inventors: Paul Master, Frederick Furtek
  • Patent number: 9760530
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 12, 2017
    Assignee: CORNAMI, INC.
    Inventors: Solomon Harsha, Paul Master
  • Patent number: 9760531
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 12, 2017
    Assignee: CORNAMI, INC.
    Inventors: Solomon Harsha, Paul Master
  • Publication number: 20170212866
    Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
    Type: Application
    Filed: April 6, 2017
    Publication date: July 27, 2017
    Inventors: Solomon Harsha, Paul Master