Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Abstract: Embodiments of the invention include a deposition machine that allows for continuous deposition of an object or substrate with a coating having a graded composition. The deposition machine includes a deposition chamber separated into a plurality of chamber areas by a baffle having an opening. The opening allows for migration of deposition material from one chamber area to another, allowing for a graded composition coating to be deposited on the object or substrate. Other embodiments include a system for forming an electronic device and a system and method for forming a graded composition on an object.

Abstract: A composite article comprises two polymeric substrate layers, each of which has at least a diffusion-inhibiting barrier on one of the surfaces. The diffusion-inhibiting barriers are disposed such that they face each other within the composite articles. Electronic devices are disposed on such composite articles to reduce the rate of diffusion of chemical species in the environment into the devices.

Abstract: An apparatus comprises a fixture comprising at least one inner member and at least one outer member. The fixture is configured to secure a film between the at least one inner member and the at least one outer member. The secured film can be further processed to give a processed film. Further, the processed film, secured in the fixture, can undergo additional manufacturing steps to produce processed articles. The apparatus and methods described herein are useful for producing a variety of articles, such as micro-electronic and opto-electronic devices.

Abstract: A substrate stack is suspended within a stack holder to position upper and lower stack surfaces coplanar with upper and lower holder surfaces. Laminating heat and pressure is simultaneously applied to the upper and lower surfaces to laminate a carrier interconnect film to top and bottom stack portions simultaneously. Subsequent wet chemical processing of both stack edges may also be simultaneous to effect savings in manufacturing costs.

Abstract: A flexible, multilayer thin film capacitor comprises a flexible substrate and at least two electrode layers mounted on the substrate alternately with at least one dielectric layer. The dielectric layer may include amorphous hydrogenated carbon. The at least two electrode layers and the at least one dielectric layer are capable of acting as at least one capacitor, and the flexible substrate is capable of being manipulated so as to have a desired shape.

Abstract: A process and configuration are described which enable the I/O metal fingers of any high density interconnect (HDI) module to be extended over the edge of a substrate at the end of circuit fabrication, thus enabling fabrication of circuits for arrangement in three-dimensional stacks. The module includes a first dielectric layer covering one or more electrical conductors on a substrate. The first dielectric layer is ablated to expose a portion of at least one electrical conductor and a second dielectric layer is then applied over the first dielectric layer and the exposed portion of the electrical conductor except for an extremity of the conductor. A second electrical conductor is subsequently applied and patterned to cover a portion of the second dielectric layer, the extremity of the conductor, and at least a portion of one edge of the substrate.

Abstract: A method of making a composite conductive structure is described. The structure includes an insulating substrate on which is provided a conductor of a refractory metal substantially nonreactive with silicon dioxide covered by a layer of a silicide of the refractory metal and a layer of silicon dioxide. The method includes depositing a layer of polycrystalline silicon over the conductor and the insulating substrate, reacting the layer of polycrystalline silicon with the conductor to form a refractory metal silicide, removing the unreacted portion of the layer of polycrystalline silicon, and then oxidizing the exposed surface of the refractory metal silicide into a layer of silicon dioxide.