Patents by Inventor Paul McGregor

Paul McGregor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8496588
    Abstract: Embodiments of the present invention are directed to methods of rapidly obtaining ultrasonic images of the eye using a set of procedural options that can be automated by a positioning mechanism that can be controlled by software.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: July 30, 2013
    Assignee: Arcscan, Inc.
    Inventors: George J. Eilers, J. David Stienmier, Wes Weber, Eric Osmann, Randy Rasmussen, Paul McGregor, Olga Medvedeva
  • Patent number: 8396363
    Abstract: A lock-in ratio measurement system including a plurality of channels. Each of the channels generates and transmits a radiation signal modulated by a sequence of tones. The sequence of tones for each channel being unique in time to that respective channel. Each respective modulated signal is absorbed/reflected from a target or medium and received. Each channel computes a lock-in value based on the received modulation signal. The lock-in values are used to compute ratios between the channels for characterizing a target or medium.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: March 12, 2013
    Assignee: Exelis, Inc.
    Inventors: Michael G. Braun, Jeremy Todd Dobler, Wayne Henry Erxleben, Douglas Paul McGregor
  • Publication number: 20100004537
    Abstract: Embodiments of the present invention are directed to methods of rapidly obtaining ultrasonic images of the eye using a set of procedural options that can be automated by a positioning mechanism that can be controlled by software.
    Type: Application
    Filed: April 3, 2009
    Publication date: January 7, 2010
    Applicant: ArcScan, Inc.
    Inventors: George J. Eilers, J. David Stienmier, Wes Weber, Eric Osmann, Randy Rasmussen, Paul McGregor, Olga Medvedeva
  • Patent number: 7438794
    Abstract: A copper electroplating bath composition and a method of copper electroplating to improve gapfill are provided. The method of electroplating includes providing an aqueous electroplating composition, comprising copper, at least one acid, at least one halogen ion, an additive including an accelerating agent, a suppressing agent, and a suppressing-accelerating agent, and the solution and mixture products thereof; contacting a substrate with the plating composition; and impressing a multi-step waveform potential upon the substrate, wherein the multi-step waveform potential includes an entry step, wherein the entry step includes a first sub-step applying a first current and a second sub-step applying second current, the second current being greater than the first current. The accelerating agent is provided in concentration of greater than 1.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: David Jentz, Ramesh Viswanathan, Paul McGregor, Valery Dubin, Rajiv Rastogi
  • Patent number: 7220674
    Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Thomas N. Marieb, Paul McGregor, Carolyn Block, Shu Jin
  • Publication number: 20060065536
    Abstract: A copper electroplating bath composition and a method of copper electroplating to improve gapfill are provided. The method of electroplating includes providing an aqueous electroplating composition, comprising copper, at least one acid, at least one halogen ion, an additive including an accelerating agent, a suppressing agent, and a suppressing-accelerating agent, and the solution and mixture products thereof; contacting a substrate with the plating composition; and impressing a multi-step waveform potential upon the substrate, wherein the multi-step waveform potential includes an entry step, wherein the entry step includes a first sub-step applying a first current and a second sub-step applying second current, the second current being greater than the first current. The accelerating agent is provided in concentration of greater than 1.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: David Jentz, Ramesh Viswanathan, Paul McGregor, Valery Dubin, Rajiv Rastogi
  • Patent number: 6977224
    Abstract: A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, and introducing a conductive shunt material through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, introducing a conductive shunt material having an oxidation number over an exposed surface of the interconnect structure, and reducing the oxidation number of the shunt. An apparatus comprising a substrate comprising a device having contact point, a dielectric layer overlying the device with an opening to the contact point, and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: December 20, 2005
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Paul McGregor, Madhav Datta
  • Patent number: 6977220
    Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: December 20, 2005
    Assignee: Intel Corporation
    Inventors: Thomas N. Marieb, Paul McGregor, Carolyn Block, Shu Jin
  • Publication number: 20040224507
    Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.
    Type: Application
    Filed: June 2, 2004
    Publication date: November 11, 2004
    Inventors: Thomas N. Marieb, Paul McGregor, Carolyn Block, Shu Jin
  • Publication number: 20040219788
    Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.
    Type: Application
    Filed: June 1, 2004
    Publication date: November 4, 2004
    Inventors: Thomas N. Marieb, Paul McGregor, Carolyn Block, Shu Jin
  • Patent number: 6800554
    Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventors: Thomas N. Marieb, Paul McGregor, Carolyn Block, Shu Jin
  • Patent number: 6794755
    Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
  • Publication number: 20040056329
    Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlaver dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.
    Type: Application
    Filed: March 25, 2003
    Publication date: March 25, 2004
    Inventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
  • Publication number: 20040056366
    Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.
    Type: Application
    Filed: September 25, 2002
    Publication date: March 25, 2004
    Inventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
  • Patent number: 6696758
    Abstract: An apparatus including a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an interconnect material and a different conductive shunt material.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: February 24, 2004
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Paul McGregor, Madhav Datta
  • Publication number: 20030071355
    Abstract: An apparatus including a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an interconnect material and a different conductive shunt material.
    Type: Application
    Filed: November 7, 2002
    Publication date: April 17, 2003
    Inventors: Valery M. Dubin, Christopher D. Thomas, Paul McGregor, Madhav Datta
  • Publication number: 20020084529
    Abstract: A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, and introducing a conductive shunt material through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, introducing a conductive shunt material having an oxidation number over an exposed surface of the interconnect structure, and reducing the oxidation number of the shunt. An apparatus comprising a substrate comprising a device having contact point, a dielectric layer overlying the device with an opening to the contact point, and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventors: Valery M. Dubin, Christopher D. Thomas, Paul McGregor, Madhav Datta
  • Publication number: 20020076925
    Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 20, 2002
    Inventors: Thomas N. Marieb, Paul McGregor, Carolyn Block, Shu Jin