Patents by Inventor Paul McKay Moore

Paul McKay Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9780204
    Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: October 3, 2017
    Assignee: Micrel, Inc.
    Inventors: Jayasimha Swamy Prasad, Paul McKay Moore, David Raymond Zinn
  • Publication number: 20170133502
    Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.
    Type: Application
    Filed: November 16, 2016
    Publication date: May 11, 2017
    Inventors: Jayasimha Swamy Prasad, Paul McKay Moore, David Raymond Zinn
  • Patent number: 9530880
    Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: December 27, 2016
    Assignee: Micrel, Inc.
    Inventors: Jayasimha Swamy Prasad, Paul McKay Moore, David Raymond Zinn
  • Publication number: 20160260831
    Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 8, 2016
    Inventors: Jayasimha Swamy Prasad, Paul McKay Moore, David Raymond Zinn
  • Patent number: 8889518
    Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: November 18, 2014
    Assignee: Micrel, Inc.
    Inventors: Martin Alter, Paul McKay Moore
  • Patent number: 8878287
    Abstract: The present invention provides an FET which includes an epitaxial layer and first and second body regions formed over the epitaxial layer. Further, the FET includes a first trench formed in the epitaxial layer between the first and the second body regions. The FET also includes a conductive layer formed on the sidewall of the first trench. The conductive layer acts as gate of the FET. The FET also includes a second trench formed at the bottom of the first trench, a first dielectric layer formed over the conductive layer and on the sidewall of the second trench, and a second dielectric layer formed on the first dielectric layer. Further, the FET includes a conductive layer, which acts as drain, deposited in the first and the second trenches. The FET also includes first and a second source regions formed in the first and second body regions, respectively.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Micrel, Inc.
    Inventor: Paul McKay Moore
  • Publication number: 20130316508
    Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.
    Type: Application
    Filed: July 30, 2013
    Publication date: November 28, 2013
    Applicant: Micrel, Inc.
    Inventors: Martin Alter, Paul McKay Moore
  • Patent number: 6916692
    Abstract: The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: July 12, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore
  • Patent number: 6577362
    Abstract: A pixel cell for a silicon LC light valve features a plurality of transparent electrically conducting pixel electrodes formed over a grounded reflective metal backplane. Dielectric material intervenes between the transparent electrodes and the grounded reflective backplane. This dielectric material, alone or in combination with the transparent electrode, creates a reflectance enhancing coating generating constructive interference of light reflected by the underlying backplane. The dielectric material also serves as the dielectric of an additional capacitive component having the active electrode and the grounded reflective metal backplane as plates. This architecture enhances the storage capacitance of the pixel cell, lowering sensitivity of the pixel to current leakage and reducing the pixel cell surface area. This pixel architecture also reduces the appearance of dark lines attributable to absorption of light in inter-pixel regions.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: June 10, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore
  • Publication number: 20020145699
    Abstract: The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.
    Type: Application
    Filed: February 6, 2002
    Publication date: October 10, 2002
    Inventor: Paul McKay Moore
  • Patent number: 6452647
    Abstract: A receiver receives a signal transmitted by a time-division multi-access method that divides one frame into a plurality of communication slots in conducting communication. In this receiver, a detection circuit detects whether a received RF signal is stronger than a predetermined level. The received RF signal is demodulated by a demodulation circuit. An oscillation circuit generates a clock that is used to decode the data obtained by demodulation. The data obtained by demodulation is stored in a memory in synchronism with a clock reproduced from the received signal, and is then retrieved from the memory in synchronism with the clock generated by the oscillation circuit. This eliminates jitters. After jitter elimination, the data is decoded by a processing circuit. The writing/reading operation against the memory is initialized in accordance with a result output from the detection circuit.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 17, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore
  • Patent number: 6356327
    Abstract: A pixel cell array for a silicon light valve positions a reflective metal surface underneath inter-pixel regions. This underlying reflective metal surface reflects incident light, thereby preventing absorption of light in inter-pixel regions that can disturb charge stored in underlying capacitors or cause dark lines to appear between electrodes. The underlying reflective metal surface can be formed as a plurality of discrete, floating, electrically-isolated structures. Alternatively, the underlying reflective metal surface can formed as a plurality of discrete structures linked to adjacent pixel electrodes through via structures. The underlying reflective metal surface can also be designed as a continuous grid including a contact for receiving an applied bias.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: March 12, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore
  • Publication number: 20010029056
    Abstract: The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.
    Type: Application
    Filed: February 28, 2001
    Publication date: October 11, 2001
    Inventor: Paul McKay Moore
  • Publication number: 20010008438
    Abstract: The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.
    Type: Application
    Filed: February 28, 2001
    Publication date: July 19, 2001
    Inventor: Paul McKay Moore
  • Patent number: 6233033
    Abstract: The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: May 15, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Paul McKay Moore
  • Patent number: 6190936
    Abstract: A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) performing alloy/sintering of the metal-silicon interface prior to a chemical mechanical polish of the intermetal dielectric before the reflective metal electrode is formed; 2) chemical-mechanical polishing the intermetal dielectric layer again after vias are formed; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: February 20, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Paul McKay Moore, Kevin Carl Brown, Richard Luttrell
  • Patent number: 6124912
    Abstract: Applying layers of dielectric material to a reflective conductive surface of an integrated circuit, increases the reflectance of the surface. The layers of dielectric material alternate between high and low indices of refraction. To enable incident light waves to undergo a uniform phase change as the waves pass between the dielectric materials, the thickness of each of the layers of dielectric material is established such that each of the layers of dielectric material have a substantially equal optical thickness. As a result, when he dielectric layers reflect incident light waves, the reflected light waves constructively interfere to increase the reflectance of the surface of the integrated circuit.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: September 26, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore
  • Patent number: 6107114
    Abstract: Reflectance of a silicon light valve is preserved by eliminating bowing in the wafer and by retaining the pad etch photoresist mask on the wafer until insertion of LC material. Wafer bowing is eliminated by performing backside etching to remove polysilicon and oxide accumulated during previous polysilicon deposition steps. The pad etch photoresist mask serves as passivation during wafer transport and testing before liquid crystal material is inserted. The pad etch photoresist mask is removed during the cleaning step that is required prior to insertion of LC material. Elimination of the redundant pad etch photoresist mask stripping step spares the metal electrodes of the precursor light valve structure from roughness and loss of reflectance that would be caused by the extra cleaning step.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: August 22, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore
  • Patent number: 6008876
    Abstract: An array of pixels in a liquid crystal silicon light valve are fabricated with a minimum of surface topology by forming raised dielectric spacer walls on an underlying array support surface prior to the deposition of the metal pixel electrode layer. Deposition of the metal pixel electrode layer, followed by chemical-mechanical polishing to stop on the top of the spacer walls, produces an electrode surface that is flush with the tops of the dielectric spacer walls. This resulting planarity in the surface of the pixel cell array minimizes surface topology exhibited by the array, maximizing reflectance of the light valve.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: December 28, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore
  • Patent number: 5982472
    Abstract: An array of pixel cells for a liquid crystal light value includes support pillars separating the array surface from a translucent top plate. During fabrication, a series of raised intersecting spacer walls having sides and a top surface are first formed by etching a thick oxide layer to stop on a nitride layer. Exposed nitride etch-stop layer is then removed, and electrode liner, metal electrode, and passivation layers are formed over the entire structure, including the sides and top surface of the spacer walls. Photoresist is then spun, hardened, and etched to expose the passivation formed over the tops of the spacer walls. The exposed passivation layer, and pixel liner and metal electrode material underneath the exposed passivation layer at the margins of the spacer walls are then etched. A photoresist mask is patterned to cover points of intersection of the spacer walls, and unmasked lengths of spacer walls are etched to stop on the nitride etch-stop layer.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: November 9, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Paul McKay Moore