Abstract: A method and system including a computer processor; an optimization module executing on the computer processor and configured to enable the computer processor to: receive a user application, where the user application includes a set of functions; simulate execution of different configurations of the set of functions on a multi-core microprocessor chip, where: the multi-core microprocessor chip includes a set of tiles arranged in a grid configuration, where each tile includes a processor core and a corresponding router, where each router is communicatively coupled with at least one other router to form a network-on-chip and each router implements a deterministic static priority routing policy, and the different configurations include execution of the set of functions by different groups of tiles; monitor network traffic patterns of the execution of the different configurations; rank the different configurations according to ranking criteria, where the ranking criteria is used to rank each of the different conf

Abstract: A system including an optimization module executing on and configured to enable a computer processor to: receive a user application including a set of functions and simulate execution of different configurations of the functions on a multi-core microprocessor chip, where: the multi-core microprocessor chip includes a set of tiles arranged in a grid configuration, where each tile includes a processor core and a corresponding router, where each router is communicatively coupled with at least one other router to form a network-on-chip and implements a deterministic static priority routing policy, and the different configurations include execution of the functions by different groups of tiles. The computer processor is further enabled to monitor network traffic patterns of the execution of the different configurations; rank the different configurations based on the corresponding network traffic patterns; and select an optimal configuration of the different configurations based on the ranking.

Abstract: A method and system including a set of processor cores; and a set of routers each including a set of input ports and a set of output ports, where: each processor core of the set of processor cores corresponds to a different router of the set of routers and is communicatively coupled with a corresponding router via the router's set of input ports and set of output ports, based on a physical destination address of a data packet, each router is operable to send one or more data packets to the one or more adjacent routers or the processor core corresponding to the router, where each router is operable to retain a data packet in the event of a traffic condition, and each router implements a deterministic routing policy.

Abstract: A method and system for implementing very long instruction words (VLIW), the system operable to: receive a first very long instruction word (VLIW) including a set of slot instructions corresponding to a set of functional units, where: each slot instruction includes an opcode identifying an operation to be performed by the set of functional units and value fields related to the operation, where a dedicated subset of the value fields include dedicated bits dedicated to the slot instruction and an allocable subset of the value fields include allocable bits allocable to other slot instructions; identify the opcodes of each slot instruction; determine, based on the opcodes, which allocable bits are allocated to which slot instructions; and instruct each functional unit to perform an operation identified by a corresponding slot instruction using the corresponding dedicated bits and any allocable bits determined to be allocated to the slot instruction.

Abstract: A method and system including a set of processor cores; and a set of routers each including a set of input ports and a set of output ports, where: each processor core of the set of processor cores corresponds to a different router of the set of routers and is communicatively coupled with a corresponding router via the router's set of input ports and set of output ports, based on a physical destination address of a data packet, each router is operable to send one or more data packets to the one or more adjacent routers or the processor core corresponding to the router, where each router is operable to retain a data packet in the event of a traffic condition, and each router implements a deterministic routing policy.

Abstract: A method and system including a computer processor; an optimization module executing on the computer processor and configured to enable the computer processor to: receive a user application, where the user application includes a set of functions; simulate execution of different configurations of the set of functions on a multi-core microprocessor chip, where: the multi-core microprocessor chip includes a set of tiles arranged in a grid configuration, where each tile includes a processor core and a corresponding router, where each router is communicatively coupled with at least one other router to form a network-on-chip and each router implements a deterministic static priority routing policy, and the different configurations include execution of the set of functions by different groups of tiles; monitor network traffic patterns of the execution of the different configurations; rank the different configurations according to ranking criteria, where the ranking criteria is used to rank each of the different conf

Abstract: A method and system for implementing very long instruction words (VLIW), the system operable to: receive a first very long instruction word (VLIW) including a set of slot instructions corresponding to a set of functional units, where: each slot instruction includes an opcode identifying an operation to be performed by the set of functional units and value fields related to the operation, where a dedicated subset of the value fields include dedicated bits dedicated to the slot instruction and an allocable subset of the value fields include allocable bits allocable to other slot instructions; identify the opcodes of each slot instruction; determine, based on the opcodes, which allocable bits are allocated to which slot instructions; and instruct each functional unit to perform an operation identified by a corresponding slot instruction using the corresponding dedicated bits and any allocable bits determined to be allocated to the slot instruction.