Abstract: A grain-boundary self-aligned resistive memory structure is provided enabling the closely-packed formation of multiple, oxide-based, ReRAM elements in parallel, each with its own compliance resistor. The structure is capable of forming multiple filaments, one per element, with the aim of reducing the variability in the composite ReRAM cell.

Abstract: To limit resistance variability across a resistive random-access memory (RRAM) call, the disclosure includes an RRAM cell with a resistance spreading layer within the RRAM cell between the top and bottom electrodes of the RRAM cell. The resistance spreading layer is in series with and has no impedance with a filament forming layer of the RRAM cell. The resistance spreading layer may be below the filament forming layer or the resistance spreading layer may be above the filament forming layer. The resistance spreading layer may further be in series with and has no impedance with the bottom electrode or the top electrode.

Abstract: A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.

Abstract: A system comprises a processor, and a resistive processing resistive processing unit coupled to the processor. The resistive processing unit comprises an array of cells, wherein the cells respectively comprise resistive memory devices, wherein at least a portion of the resistive memory devices are programmable to store weight values of a given matrix in the array of cells. The processor is configured to store the given matrix in the array of cells of the resistive processing unit, and perform a calibration process to generate a first set of calibration parameters for calibrating forward pass matrix-vector multiplication operations performed on the stored matrix in the array of cells of the resistive processing unit, and a second set of calibration parameters for calibrating backward pass matrix-vector multiplication operations performed on a transpose of the stored matrix in the array of cells of the resistive processing unit.

Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.

Abstract: An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.

Abstract: An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.

Abstract: Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.

Abstract: A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

Abstract: A processing unit, including a first circuit part, and a capacitor connected to the first circuit part. The capacitor is charged or discharged by the first circuit part.

Abstract: A vertical injection punchthrough based metal oxide semiconductor (VIPMOS) device and method of manufacturing the same, include a control gate, an erase gate, a floating gate, and an active area where the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area.

Abstract: Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.

Abstract: A processing unit, including a first circuit part, and a capacitor connected to the first circuit part. The capacitor is charged or discharged by the first circuit part.

Abstract: A processing unit includes a circuit including a current mirror, and a capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by the current mirror.

Abstract: A vertical injection punchthrough based metal oxide semiconductor (VIPMOS) device and method of manufacturing the same, include a control gate, an erase gate, a floating gate, and an active area where the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area.

Abstract: A processing unit includes a circuit including a current mirror, and a capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by the current mirror.

Abstract: A resistive processing unit (RPU) includes a circuit including at least two current mirrors connected in series, and a capacitor connected with the at least two current mirrors, the capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by one of the at least two current mirrors.

Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.