Abstract: An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Abstract: An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Abstract: An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Abstract: An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Abstract: An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Abstract: An image sensor of a camera system captures an image over an image capture interval of time, and waits a blanking interval of time before capturing an additional image. The captured image is provided to a frame controller, and is buffered until an image signal processor accesses the captured image. The image signal processor processes the accessed image over an image processing interval of time, producing a processed image. The image processing interval of time is selected to be greater than the image capture interval of time, but less than the sum of the image capture interval of time and the blanking interval of time. By reducing the image capture interval of time but maintaining an image processing interval of time, rolling shutter artifacts are beneficially reduced without increasing the processing resources or power required by the image signal processor to process the image.

Abstract: An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Abstract: A system and method are provided for packing compressed image data into a format suitable for encoding. The system includes a plurality of sub-band state registers, which store compressed image data from a corresponding sub-band. A bit packer receives a stream of bits of compressed image data, and concatenates the input bits with bits stored in one of the sub-band state registers. If a length of the concatenated bits is less than a width of an output data bus, the bit packer stores the concatenated bits in the sub-band state register. If the length of the concatenated bits is greater than or equal to the width of the output data bus, the bit packer outputs the concatenated bits via the output data bus.

Abstract: An image sensor of a camera system captures an image over an image capture interval of time, and waits a blanking interval of time before capturing an additional image. The captured image is provided to a frame controller, and is buffered until an image signal processor accesses the captured image. The image signal processor processes the accessed image over an image processing interval of time, producing a processed image. The image processing interval of time is selected to be greater than the image capture interval of time, but less than the sum of the image capture interval of time and the blanking interval of time. By reducing the image capture interval of time but maintaining an image processing interval of time, rolling shutter artifacts are beneficially reduced without increasing the processing resources or power required by the image signal processor to process the image.