Abstract: Vehicle for aeronautic operation and submersed operation includes members secured to rotors and a body, the members having adjustable features arranged and disposed to position the rotors to rotate in a first plane during the aeronautic operation and a second plane during the submersed operation, a fluid enclosure operably connected through the body to the rotor, the fluid enclosure having a submersion mechanism arranged and disposed for the vehicle to adjustably ascend and descend during the submersed operation of the vehicle, and a control system and power system for operably controlling the rotor, the adjustable feature, and/or the fluid enclosure. The rotor is configured to move the vehicle during the aeronautic operation and the submersed operation. A process includes operating the vehicle in the aeronautic operation and the submersed operation.

Abstract: A compartmentalized cooler is provided. The cooler may have partitions capable of isolating different compartments of the cooler from the other. These partitions may have additional functions such as acting as a cutting board or ice pack. The cooler may further have a lock box contained within one of the partitions.

Abstract: Disclosed are two mechanisms for preventing access failures attributable to dynamic port assignment of firewall-blocked ports. The mechanism involves an enhanced firewall that opens blocked ports prior to possible dynamic allocation so that the blocked ports are not available when a port is requested. The second mechanism involves an enhanced commutations stack that works in conjunction with an enhanced firewall to reserve blocked ports so that the blocked ports are not available for dynamic allocation when a port is requested.

Abstract: An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region. In another embodiment a first device region, is formed on a semiconductor layer.

Abstract: Disclosed are two mechanisms for preventing access failures attributable to dynamic port assignment of firewall-blocked ports. The mechanism involves an enhanced firewall that opens blocked ports prior to possible dynamic allocation so that the blocked ports are not available when a port is requested. The second mechanism involves an enhanced commutations stack that works in conjunction with an enhanced firewall to reserve blocked ports so that the blocked ports are not available for dynamic allocation when a port is requested.

Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material.

Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices.

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers.

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer.After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material.

Abstract: A capacitor charging circuit for charging a defibrillation capacitor in a constant period of time regardless of battery voltage by employing a controlled duty cycle charging technique. The defibrillation capacitor is charged in a piecemeal manner through a transistor and flyback transformer circuit. The gate of the transistor is driven by a constant frequency pulse train inverter drive signal in which voltage is conveyed to the capacitors during one-half of the full cycle of the pulse train. The primary of the transformer is controlled by each pulse of the inverter drive signal so that the secondary of the transformer supplies current to the defibrillation capacitors during the off half cycle of the drive signal, the charge being built up in the defibrillation capacitors incrementally during the off half cycle of the inverter drive signal until the predetermined voltage is reached.

Abstract: A temporary pacemaker combines technologies of the implantable pacemaker, the waterproof watch, with a separate remote-control programming unit that communicates with the pacemaker via IR radiation. An LCD readout on the temporary pacemaker continuously reports on current settings, and is monitored periodically, as well as during the setting process. The programming unit is aimed at an IR sensor on the pacemaker, and its dedicated controls are used for setting, with the aid of prompting messages on its own LCD panel. Battery life is about 6-9 months, while that for the lithium battery in the sealed and sterilizable pacemaker approaches five years.A multi-conductor connector and an adapter for use with a temporary external pacemaker, is disclosed which reduces the complexity of connecting temporary pacing leads, adapters, extension cables, heart wires or other miscellaneous cables to a pacing device.

Abstract: A remote temperature sensing and warning system for a temperature controlled vehicle comprising a remote temperature sensing unit for measuring the temperature in the transport container and transmitting the temperature signal within a repeating time frame through the existing vehicle wiring to a remote receiver; the receiver decoding and converting the signal into a displayable form to continuously display the current temperature of the transport container; the receiver further detecting out of range temperatures and signal transmission errors and providing visual and aural alarms therefrom.