Abstract: Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.

Abstract: The manufacture of an integrated circuit chip includes testing the integrated circuit while an external electric field is applied to the integrated circuit to facilitate detection of open circuit type defects. The electric field may be provided by applying a high potential to a plate parallel to a plane of the integrated circuit or by applying a high potential to a probe and moving the probe across the surface of the integrated circuit chip to obtain information regarding the location of the defect. Use of a probe type electric field generator allows the approximate position of the defect to be determined. The invention enhances current testing and diagnostics methods for wafers, chips, and integrated circuit packages by allowing detection of floating net defects during other conventional tests.

Abstract: The manufacture of an integrated circuit chip includes testing the integrated circuit while an external electric field is applied to the integrated circuit to facilitate detection of open circuit type defects. The electric field may be provided by applying a high potential to a plate parallel to a plane of the integrated circuit or by applying a high potential to a probe and moving the probe across the surface of the integrated circuit chip to obtain information regarding the location of the defect. Use of a probe type electric field generator allows the approximate position of the defect to be determined. The invention enhances current testing and diagnostics methods for wafers, chips, and integrated circuit packages by allowing detection of floating net defects during other conventional tests.