Patents by Inventor Paul Murrin
Paul Murrin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11755474Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.Type: GrantFiled: November 18, 2021Date of Patent: September 12, 2023Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
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Publication number: 20220075723Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.Type: ApplicationFiled: November 18, 2021Publication date: March 10, 2022Inventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
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Patent number: 11210217Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.Type: GrantFiled: April 10, 2020Date of Patent: December 28, 2021Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
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Patent number: 11184110Abstract: Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.Type: GrantFiled: November 2, 2020Date of Patent: November 23, 2021Assignee: Imagination Technologies LimitedInventors: Filipe Carvalho, Paul Murrin
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Patent number: 11044128Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.Type: GrantFiled: July 6, 2020Date of Patent: June 22, 2021Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Adrian John Anderson
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Publication number: 20210050942Abstract: Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.Type: ApplicationFiled: November 2, 2020Publication date: February 18, 2021Inventors: Filipe Carvalho, Paul Murrin
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Patent number: 10862624Abstract: Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.Type: GrantFiled: June 29, 2019Date of Patent: December 8, 2020Assignee: Imagination Technologies LimitedInventors: Filipe Carvalho, Paul Murrin
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Publication number: 20200336346Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Inventors: Paul Murrin, Adrian John Anderson
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Patent number: 10756935Abstract: A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.Type: GrantFiled: August 22, 2019Date of Patent: August 25, 2020Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Adrian John Anderson
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Patent number: 10742460Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.Type: GrantFiled: August 22, 2019Date of Patent: August 11, 2020Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Adrian John Anderson
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Publication number: 20200242029Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
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Patent number: 10657050Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.Type: GrantFiled: April 11, 2019Date of Patent: May 19, 2020Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
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Publication number: 20200067742Abstract: A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.Type: ApplicationFiled: August 22, 2019Publication date: February 27, 2020Inventors: Paul Murrin, Adrian John Anderson
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Publication number: 20200067741Abstract: A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm.Type: ApplicationFiled: August 22, 2019Publication date: February 27, 2020Inventors: Paul Murrin, Adrian John Anderson
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Publication number: 20200007273Abstract: Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.Type: ApplicationFiled: June 29, 2019Publication date: January 2, 2020Inventors: Filipe Carvalho, Paul Murrin
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Patent number: 10387155Abstract: A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. While the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.Type: GrantFiled: March 24, 2016Date of Patent: August 20, 2019Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Gareth Davies, Adrian J. Anderson
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Publication number: 20190236006Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.Type: ApplicationFiled: April 11, 2019Publication date: August 1, 2019Inventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
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Patent number: 10296456Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.Type: GrantFiled: March 12, 2013Date of Patent: May 21, 2019Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Adrian J. Anderson, Mohammed El-Hajjar
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Patent number: 10255161Abstract: A logging unit is used to log entries for events in a computer system. Each entry includes an n-bit timestamp field and a payload. The payload includes information about the event and the timestamp field includes the n least significant bits of an N-bit timestamp for the event, where N>n. If the n least significant bits of the timestamp have wrapped compared to the corresponding n bits of the timestamp of the preceding entry then a timing entry is logged which includes other bits of the timestamp. Therefore, an N-bit timestamp can be determined for an event, but only the n least significant bits of the timestamp are stored in the timestamp field of an entry for the event. Therefore, the time flow of events in the store is better maintained (by having a larger timestamp) without increasing the number of bits (n) in the timestamp field of each entry.Type: GrantFiled: March 24, 2016Date of Patent: April 9, 2019Assignee: Imagination Technologies LimitedInventors: Paul Murrin, Gareth Davies
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Patent number: 10142154Abstract: Methods and OFDM receivers for decoding an OFDM signal include estimating a channel impulse response from a pilot-dense symbol of the OFDM signal for each of a plurality of potential FFT window positions; determining a noise floor of each of the channel impulse responses; selecting the potential window position corresponding to the channel impulse response with the lowest noise floor as an optimum FFT window position; and decoding symbols of the OFDM signal using the optimum FFT window position.Type: GrantFiled: March 14, 2018Date of Patent: November 27, 2018Assignee: Imagination Technologies LimitedInventors: Mohammed Alloulah, Paul Murrin, Alamo Spaargaren