Abstract: A method for simultaneously forming a level of interconnection metallurgy over, and inter-level via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, high-mobility sputtering conductive material on to the surface of the insulating layer and into the via holes therein, masking the conductive material layer, and then ion beam milling through the mask to form a patterned interconnection layer. The high-mobility sputtering step is accomplished by reducing the background pressure to below 10.sup.-7 Torr to eliminate non-mobile species, maintaining a sputter pressure of less than 7 microns, maintaining an appropriate chip bias level to keep the conductive material molecules mobile until they reach their lowest energy state, and maintaining the temperature of the chip at a level so that a high sputter species mobility is maintained.

Abstract: Three-dimensional polymerization of resin glass on an underlay surface may cause uneven distribution of the layer and therefore uneven etching of the glass layer in subsequent processing. The glass remaining after an etching step can cause difficulties in further processing of the structure, such as causing metal opens in a metallization step. In order to control the three-dimensional polymerization; the underlay surface is treated with a short plasma treatment. The plasma oxidizing step renders the surface acidic, forcing the glass polymerization to occur in a two-dimensional mode thereby eliminating the threat of uneven distribution and its repercussions.