Abstract: In a particular embodiment, a method of anticipatorily loading a page of memory is provided. The method may include, during execution of first program code using a first page of memory, collecting data for at least one attribute of the first page of memory, including collecting data about at least one next page of memory that interacts with the first page of memory for a historical topology attribute of the first page of memory. The method may also include, during execution of second program code using the first page of memory, determining a second page of memory to anticipatorily load based on the historical topology attribute of the first page of memory.

Abstract: A method of dynamic energy management that includes loading an energy budget configuration stream for an instruction of a thread, loading characterization data for the thread, computing energy management settings for the instruction based on the characterization data and the budget configuration stream, and driving control signals indicative of the computed energy management settings.

Abstract: In a particular embodiment, a method of anticipatorily loading a page of memory is provided. The method may include, during execution of first program code using a first page of memory, collecting data for at least one attribute of the first page of memory, including collecting data about at least one next page of memory that interacts with the first page of memory for a historical topology attribute of the first page of memory. The method may also include, during execution of second program code using the first page of memory, determining a second page of memory to anticipatorily load based on the historical topology attribute of the first page of memory.

Abstract: A method of dynamic energy management that includes loading an energy budget configuration stream for an instruction of a thread, loading characterization data for the thread, computing energy management settings for the instruction based on the characterization data and the budget configuration stream, and driving control signals indicative of the computed energy management settings.

Abstract: A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.

Abstract: System and computer-implemented methods herein design a configurable pipelined processor. Such systems and methods provide a configuration specification, by providing a base processor or digital design description, a base instruction set with a plurality of base instructions, and a plurality of configurable features. At least one of the configurable features is an additional instruction different from the base instructions. Further, such systems and methods generate a hardware implementation based on the configuration specification to produce a plurality of configured pipeline stages. The configured pipeline stages are different from base pipeline stages in a base processor or digital design hardware implementation (corresponding to the base processor or digital design description as a result of the additional instruction being included in the configuration specification).

Abstract: Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

Abstract: A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.

Abstract: Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.