Abstract: A network system includes a first device and a second device coupled to each other that mux and demux data for LSL to HSL transitions. The muxing and demuxing function in the first and second device, respectively, use timing logic from an existing training protocol, such as link training (“LT”). Although LT is used for establishing links between two chips, and has no provision for maintaining port coherency for port-specific input data on one chip to port-specific output data on another chip, the LT does have a uniquely identifiable logic transition in a known data pattern used for LT that can be multi-purposed for syncing the muxing and demuxing of the two interfaced chips, using a predetermined port sequence on both chips to maintain coherency of port-specific data.