Patents by Inventor Paul Ou Yang

Paul Ou Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
    Patent number: 8049281
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: November 1, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
  • Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
    Patent number: 7935603
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: May 3, 2011
    Assignees: HRL Laboratories, LLC, Raytheon Corporation, Promtek
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
  • Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
    Patent number: 7242063
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: July 10, 2007
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
  • Multilayered integrated circuit with extraneous conductive traces
    Patent number: 6924552
    Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: August 2, 2005
    Assignees: HRL Laboratories, LLC, Promtek
    Inventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr., Paul Ou Yang
  • Multilayered integrated circuit with extraneous conductive traces
    Publication number: 20040119165
    Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.
    Type: Application
    Filed: October 14, 2003
    Publication date: June 24, 2004
    Inventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Paul Ou Yang