Abstract: An interconnect delay test uses the IEEE 1149.1 standard test access port (TAP) controller. No modification of standard boundary cells is required. Since the standard boundary scan cells are used, circuit board and/or backplane interconnect delay tests do not affect ASIC (application specific integrated circuit) designs. It allows board and system designers to add new interconnect AC tests for any signals at any time without modification of ASICs. Since the method has no impact on the operations of the standard TAP controller, it is possible to use available test softwares for interconnect DC tests to perform the proposed delay test. The method can also be integrated as part of in-system interconnect tests.