Patents by Inventor Paul Paternoster
Paul Paternoster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11036253Abstract: A circuit includes a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency. A secondary clock generation circuit is configured to generate a second clock signal having a second frequency lower than the first frequency. A voltage detection circuit is coupled to receive a supply voltage and configured to detect a droop in the supply voltage and generate a clock control signal in response to detecting a droop in the supply voltage. A selection circuit is coupled to the voltage detection circuit to receive the clock control signal and is configured to select one of the first clock signal and the second clock signal based on the clock control signal.Type: GrantFiled: September 30, 2020Date of Patent: June 15, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Paul Paternoster, Sharat Ippili
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Patent number: 9436844Abstract: A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.Type: GrantFiled: August 29, 2013Date of Patent: September 6, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Michael Love, Walker Robb, Avdhesh Chhodavdia, Paul Paternoster
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Publication number: 20150095661Abstract: Regions of system memory in a computer system are managed to maintain privacy and integrity of data. A system address space for memory is divided into a plurality of aliased addressed spaces. Each of the aliased address spaces is associated with its own unique encryption key. The system address space is managed using the aliased address spaces to provide data isolation and privacy for different system processes. One or more aliased address spaces can be provided with additional data integrity capabilities. Data associated with an integrity-checked aliased address space is subjected to data integrity checking, using authentication-based techniques such as hashing, for example. Additionally, a set of contiguous addresses in the aliased address space is defined, while being mapped to a set of non-contiguous addresses in the corresponding physical address space for additional data security.Type: ApplicationFiled: September 30, 2013Publication date: April 2, 2015Applicant: Microsoft CorporationInventors: John V. Sell, Ling Tony Chen, Paul Paternoster
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Publication number: 20150067771Abstract: A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Microsoft CorporationInventors: Michael Love, Walker Robb, Avdhesh Chhodavdia, Paul Paternoster
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Patent number: 8347251Abstract: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.Type: GrantFiled: December 31, 2007Date of Patent: January 1, 2013Assignee: SanDisk CorporationInventors: Paul Paternoster, Vaibhavi Sabharanjak, Po-Shen Lai
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Patent number: 8304813Abstract: A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.Type: GrantFiled: January 8, 2007Date of Patent: November 6, 2012Assignee: SanDisk Technologies, Inc.Inventors: Paul Lassa, Paul Paternoster, Brian Cheung
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Patent number: 8135944Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits.Type: GrantFiled: March 14, 2007Date of Patent: March 13, 2012Assignee: SanDisk Technologies Inc.Inventors: Paul Lassa, Paul Paternoster, Po-Shen Lai, Yongliang Wang
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Publication number: 20090166679Abstract: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Paul Paternoster, Vaibhavi Sabharanjak, Po-Shen Lai
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Publication number: 20080229121Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits.Type: ApplicationFiled: March 14, 2007Publication date: September 18, 2008Inventors: Paul Lassa, Paul Paternoster, Po-Shen Lai, Yongliang Wang
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Publication number: 20080164615Abstract: A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Inventors: Paul Lassa, Paul Paternoster, Brian Cheung
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Publication number: 20080162954Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits.Type: ApplicationFiled: December 31, 2006Publication date: July 3, 2008Inventors: Paul Lassa, Paul Paternoster, Po-Shen Lai, Yongliang Wang
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Publication number: 20080162957Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits.Type: ApplicationFiled: December 31, 2006Publication date: July 3, 2008Inventors: Paul Lassa, Paul Paternoster, Po-Shen Lai, Yongliang Wang
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Patent number: 6219070Abstract: A method and system for simulating motion of a polygon on a display screen. The polygon may be included in a set of polygons used to model a three-dimensional object. The position of the polygon is defined by vertices tracked in a subpixel coordinate system existing in a computer-readable medium. The subpixel coordinates of the vertices are used to identify the pixels on the display screen having coordinates that correspond to subpixel coordinates lying within or, optionally, at the boundary of the polygon. The identified pixels are those that are to be lighted on the display screen to generate the image of the polygon. The display properties of the lighted pixels are selected by interpolation based on defined pixel display parameters assigned to the vertices of the triangle. As motion of the polygon is tracked in the subpixel coordinate system, the corresponding display on the display screen is repeatedly adjusted.Type: GrantFiled: September 30, 1998Date of Patent: April 17, 2001Assignee: WebTV Networks, Inc.Inventors: Nick Baker, Adam Malamy, Adrian Sfarti, Paul Paternoster, Padma Parthasarathy
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Patent number: 5339408Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.Type: GrantFiled: December 30, 1992Date of Patent: August 16, 1994Assignee: Digital Equipment CorporationInventors: William Bruckert, Thomas D. Bissett, Glenn Dearth, Paul Paternoster