Patents by Inventor Paul Penzes

Paul Penzes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804906
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 13, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 10505541
    Abstract: A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Albert Kumar, Ramaprasath Vilangudipitchai, Vasisht Vadi, Paul Penzes
  • Publication number: 20190107569
    Abstract: Aspects of the disclosure includes a transistor-under-test (TUT) to charge/discharge a capacitor; changing an oscillation state when a capacitor voltage crosses a threshold and turning OFF the TUT; discharging the capacitor using the TUT; commencing precharging the capacitor after detecting the capacitor reaches a transition voltage; commencing discharging the capacitor after a precharger time delay; sustaining a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF/ON the TUT; and generating a digital representation of a TUT current associated with a relaxation oscillator period of the relaxation oscillator waveform.
    Type: Application
    Filed: October 11, 2017
    Publication date: April 11, 2019
    Inventors: David Kidd, Ardavan Moassessi, Angelo Pinto, Albert Kumar, Yi Lou, Bipin Duggal, Amar Gulhane, Michael Bourland, Mustafa Badaroglu, Paul Penzes
  • Publication number: 20190058477
    Abstract: A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.
    Type: Application
    Filed: August 18, 2017
    Publication date: February 21, 2019
    Inventors: Albert KUMAR, Ramaprasath VILANGUDIPITCHAI, Vasisht VADI, Paul PENZES
  • Publication number: 20180309455
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Paul PENZES, Mark FULLERTON
  • Patent number: 10033391
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 24, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Paul Penzes, Mark Fullerton
  • Publication number: 20160226498
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Applicant: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 9407272
    Abstract: Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 2, 2016
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton, Hwisung Jung, John Walley, Tim Sippel, Love Kothari
  • Patent number: 9337146
    Abstract: A particular three-dimensional integrated circuit stack includes a first die including a first bonding interface and a first plurality of interconnect layers arranged according to a first Manhattan wiring scheme. The three-dimensional integrated circuit stack also includes a second die including a second bonding interface and a second plurality of interconnect layers arranged according to a second Manhattan wiring scheme. The first die and the second die stacked with the first bonding interface coupled to the second bonding interface such that the first Manhattan wiring scheme and the second Manhattan wiring scheme are non-Manhattan with respect to each other.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 10, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Wei Yi, Yi Lou, Paul Penzes, Pranjal Srivastava
  • Patent number: 9312862
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 12, 2016
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 9209816
    Abstract: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 8, 2015
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 9007095
    Abstract: An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 14, 2015
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8957716
    Abstract: An integrated circuit cell includes a set of circuit elements associated with a logic function along a logical path between an input and an output of the integrated circuit cell. The set of circuit elements includes a first subset of circuit elements having a first width size and a first threshold voltage and configured to operate within a cycle of time. The set of circuit elements also includes a second subset of circuit elements having a second width size and a second threshold voltage and configured to operate within the cycle of time. The first subset and second subset of circuit elements are configured to toggle data between the input and the output. The second threshold voltage is less than the first threshold voltage when the second width size is less than the first width size.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 17, 2015
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8878303
    Abstract: A method of optimizing a layout of an integrated circuit formed using fin-based cells of a standard cell library is provided. The method includes arranging cell rows of different track heights having standard cells. For each cell row, each of the standard cells includes sub-cell rows with sub-cells of one or more types. The sub-cells are interchangeable with one another to modify a device characteristic of the standard cell. The method also includes evaluating the integrated circuit to determine whether a performance metric of the integrated circuit has been satisfied. The method also includes identifying one or more standard cells to modify a device characteristic of the standard cell for satisfying the performance metric of the integrated circuit. The method further includes modifying the one or more standard cells until the performance metric of the integrated circuit is satisfied.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: November 4, 2014
    Assignee: Broadcom Corporation
    Inventors: Mehdi Hatamian, Paul Penzes
  • Publication number: 20140266365
    Abstract: A circuit for a low latency, low area, and low power flip-flop may include a pass-gate multiplexer that can selectively allow one of input or test data to enter a master cell when a clock signal is low. The master cell may include a first inverter cross-coupled to a second inverter, and may receive the input or test data and may latch and provide at an input node of the slave cell, an inverted input data or the test data, upon a transition of the clock signal to a high state. The slave cell may include a second clock pass-gate and a third inverter that is cross-coupled to a fourth inverter, and may receive the inverted input data or the test data and may latch and provide at an output node, the input data or the test data, upon the transition of the clock signal to a high state.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Paul Penzes, Ardavan Moassessi
  • Patent number: 8837190
    Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 16, 2014
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8788998
    Abstract: A standard cell library for designing integrated circuits is provided. In some aspects, the standard cell library includes a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library. The standard cell library further includes a plurality of landing pins for connecting to the routing tracks arranged in the plurality of standard cells, wherein each of the plurality of landing pins is extended by half of the wiring pitch in opposite directions orthogonal to an orientation of the routing tracks.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Broadcom Corporation
    Inventors: Mehdi Hatamian, Paul Penzes
  • Publication number: 20140183646
    Abstract: A method of optimizing a layout of an integrated circuit formed using fin-based cells of a standard cell library is provided. The method includes arranging cell rows of different track heights having standard cells. For each cell row, each of the standard cells includes sub-cell rows with sub-cells of one or more types. The sub-cells are interchangeable with one another to modify a device characteristic of the standard cell. The method also includes evaluating the integrated circuit to determine whether a performance metric of the integrated circuit has been satisfied. The method also includes identifying one or more standard cells to modify a device characteristic of the standard cell for satisfying the performance metric of the integrated circuit. The method further includes modifying the one or more standard cells until the performance metric of the integrated circuit is satisfied.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 3, 2014
    Applicant: Broadcom Corporation
    Inventors: Mehdi HATAMIAN, Paul Penzes
  • Publication number: 20140181774
    Abstract: A standard cell library for designing integrated circuits is provided. In some aspects, the standard cell library includes a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library. The standard cell library further includes a plurality of landing pins for connecting to the routing tracks arranged in the plurality of standard cells, wherein each of the plurality of landing pins is extended by half of the wiring pitch in opposite directions orthogonal to an orientation of the routing tracks.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Mehdi HATAMIAN, Paul Penzes
  • Publication number: 20140167815
    Abstract: An integrated circuit using area reconfigurable cells of a standard cell library includes standard cells placed adjacent with one another in rows and columns. Each of the standard cells has a boundary type and each has a body having a first pair of opposite sides and a second pair of opposite sides orthogonal to the first pair of opposite sides. Each standard cell also has a spacer located adjacent to each of the first pair of opposite sides of the body. The spacer has a spacer type that corresponds to the boundary type of the standard cell. The spacer is removable from the standard cell when the spacer has a spacer type that matches another spacer of an adjacent standard cell.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: BROADCOM CORPORATION
    Inventor: Paul PENZES