Patents by Inventor Paul Poenisch

Paul Poenisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5985692
    Abstract: A method for flip-chip bonding an integrated circuit die to a substrate. The method includes the steps of providing the integrated circuit die with at least one gold bump, forming a barrier layer on the gold bump, forming a bronzing agent on the barrier layer, and providing the substrate with at least one conductive bonding area, which is also covered with gold. The bronzing agent on the integrated circuit die is then aligned on the conductive bonding area, and a compression force is applied to the die and substrate so as to establish contact between the bronzing agent and the conductive bonding area. While maintaining position between the gold bump and conductive bonding area, the structure is alloyed such that the bronzing agent and the gold on the conductive bonding area form an intermetallic compound, thereby forming a bond between the die and the substrate. The barrier layer functions to prevent the bronzing agent from diffusing with the gold bump.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 16, 1999
    Assignee: MicroUnit Systems Engineering, Inc.
    Inventors: Paul Poenisch, James A. Matthews, Trancy Tsao
  • Patent number: 5021980
    Abstract: A method for determination of the true temperature T and true radiative emissivity of a body at temperature T, using measurements of total energy radiated by the body in two or more adjacent wave length ranges .lambda..sub.1 .ltoreq..lambda..ltoreq..lambda..sub.2 and .lambda..sub.3 .ltoreq..lambda..ltoreq..lambda..sub.4 ; the wave length ranges may partially overlap or may be adjacent but non-overlapping.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: June 4, 1991
    Assignee: LSI Logic Corporation
    Inventors: Paul Poenisch, Keith Hansen
  • Patent number: 4374915
    Abstract: A wafer marker is described for aligning masks with the wafer. The marker comprises a depression in the wafer which is defined by sloped sides and a pitted bottom. The sloped sides and pitted bottom do not directly reflect light as does the surface of the surrounding silicon and thus the marker appears as a darker region. The bottom of the depression is pitted by exposing the anode during a silicon plasma etching step.
    Type: Grant
    Filed: July 30, 1981
    Date of Patent: February 22, 1983
    Assignee: Intel Corporation
    Inventors: C. Norman Ahlquist, Yaw Wen Hu, Peter F. Schoen, Paul A. Poenisch