Abstract: An integrated circuit (IC), including: a set of cascaded clock gating control (CGC) circuits, wherein a first one of the set of cascaded CGC circuits includes a clock input configured to receive a clock signal; an observation flip-flop including a clock input coupled to a clock output of a last one of the set of cascaded CGC circuits; an input register configured to provide logic zeros (0s) to clock enable (CE) inputs of the set of cascaded CGC circuits pursuant to a stuck-at-one (SA1) fault testing on the CE input of a selected one of the set of cascaded CGC circuits; and a set of one or more test enable (TE) control registers configured to provide one or more logic ones (1s) to one or more TE inputs of one or more of the set of cascaded CGC circuits not undergoing the stuck-at-one (SA1) fault testing, respectively.

Abstract: An on-chip clock controller includes a primary clock gating cell and a secondary clock gating cell. The primary clock gating cell includes a first clock input terminal coupled to receive an input clock signal and a first enable input terminal coupled to receive an enable signal. The primary clock gating cell also include a first clock output terminal configured to generate a first output clock signal based at least in part on the input clock signal and the enable signal. The secondary clock gating includes a second clock input terminal coupled to receive the input clock signal and a second clock output terminal configured to generate a second output clock signal based at least in part on the input clock signal. The enable signal is based at least in part on the second output clock signal.