Patents by Inventor Paul Qu

Paul Qu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970764
    Abstract: A method for producing a structure containing an array of MWCNTs on a metal substrate, comprising: (i) subjecting a metal substrate to a surface oxidation process at a first elevated temperature in an oxygen-containing atmosphere and under a first reduced pressure; (ii) subjecting the metal substrate to a surface reduction process at a second elevated temperature in a reducing atmosphere and under a second reduced pressure of at least 0.01 atm and less than 1 atm to result in reduction of the surface of said metal substrate, wherein the reducing atmosphere contains hydrogen gas; (iii) subjecting the metal substrate to a third reduced pressure of no more than 0.1 atm; and (iv) contacting the metal substrate, while at the third reduced pressure and under an inert or reducing atmosphere, with an organic substance at a third elevated temperature for suitable time to produce the MWCNTs on the metal substrate.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: April 30, 2024
    Assignee: UT-Battelle, LLC
    Inventors: Chanaka Kapila Kumara Ihala Gamaralalage, Jun Qu, Paul A. Menchhofer
  • Patent number: 11837476
    Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 5, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu
  • Publication number: 20230371185
    Abstract: A method of soldering one or more components to a substrate includes providing a substrate and applying an amount of solder material to the top planar surface of the substrate. One or more electrical components are mounted to the solder material in a predetermined position and orientation. A carrier is provided having one or more magnets embedded therein. The substrate is positioned above the carrier such that each of the one or more magnets is positioned directly below a corresponding electrical component. A carrier cover is positioned above the substrate and the electrical components. The solder material is heated to a predetermined temperature for a predetermined amount of time during which each of the magnets exerts a magnetic force on a corresponding electrical component to maintain its orientation relative to the substrate. The magnets reduce the occurrence of tombstoning of the electrical components during heating of the solder material.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Virgil Zhu, Vincent Jiang, Paul Qu, Shixing Zhu, Yuanheng Zhang, Enoch He, Yonglong Liu, Lian Chen, Guangqiang Li, Jingyun Chen
  • Publication number: 20220285316
    Abstract: A memory device includes a substrate, a controller die, a flip chip die, first and second silicon dies, and bond wires. The controller and flip chip dies are attached to the substrate using connection balls and in electrical communication with each other. The first and second silicon dies include respective first and second contact pad surfaces. The bond wires electrically connect the contact pad surfaces to the substrate so the first and second silicon dies communicate with the controller die. The flip chip die and first and second silicon dies are NAND dies, the flip chip die is configured as SLC memory, and the silicon dies are configured as one of MLC memory, TLC memory, or QLC memory.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Inventors: Rui Yuan, Hope Chiu, Paul Qu, Kevin Du, Zengyu Zhou, Yi Su, Shixing Zhu
  • Publication number: 20220093559
    Abstract: A packaged semiconductor includes a substrate and a first component disposed on the substrate. The package includes an underfill that is dispensed under and around the first component. The package also includes a second component disposed on the substrate adjacent to the first component that provides a border to the underfill.
    Type: Application
    Filed: September 22, 2020
    Publication date: March 24, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kevin Du, Hope Chiu, Zengyu Zhou, Alex Zhang, Vincent Jiang, Shixing Zhu, Paul Qu, Yi Su, Rui Yuan
  • Publication number: 20210335628
    Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.
    Type: Application
    Filed: May 15, 2020
    Publication date: October 28, 2021
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu